Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2006-09-28
2009-10-13
Rose, Kiesha L (Department: 2891)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S423000
Reexamination Certificate
active
07601606
ABSTRACT:
The invention provides methods for reducing trap densities at interfaces in a multilayer semiconductor wafer, specifically trap densities between an active layer and an insulating layer under the active layer. The methods comprise exposing wafers to high temperatures in a generally neutral atmosphere that also comprises one or more species that can, or whose ions can, migrate into the wafer down to the interface where reduction of the trap density is desired.
REFERENCES:
patent: 6136727 (2000-10-01), Ueno
patent: 6140157 (2000-10-01), Warren et al.
patent: 6204205 (2001-03-01), Yu et al.
patent: 6309968 (2001-10-01), Chu et al.
patent: 6358866 (2002-03-01), Stesmans et al.
patent: 6603156 (2003-08-01), Rim
patent: 6649538 (2003-11-01), Cheng et al.
patent: 6737730 (2004-05-01), Lane et al.
patent: 2003/0013266 (2003-01-01), Fukuda et al.
patent: 2003/0129817 (2003-07-01), Visokay et al.
patent: 2004/0126939 (2004-07-01), Baniecki et al.
patent: 2005/0079664 (2005-04-01), Faris
patent: 2006/0094259 (2006-05-01), Gilmer et al.
Schjølberg-Henriksen, K. et al., “Oxide Charges Induced By Plasma Activation For Wafer Bonding”, Sensors and Actuators, vol. A 102, pp. 99-105 (2002).
Colinge, J. P., “Silicon-On-Insulator Technology”, Materials to VLSI, 2nd Edition, pp. 50-51 (1997).
Brunier Francois
Renauld Vivien
Waechter Jean Marc
Rose Kiesha L
S.O.I.Tec Silicon on Insulator Technologies
Tornow Mark W
Winston & Strawn LLP
LandOfFree
Method for reducing the trap density in a semiconductor wafer does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for reducing the trap density in a semiconductor wafer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for reducing the trap density in a semiconductor wafer will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4100653