Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-06-26
2007-06-26
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
11248605
ABSTRACT:
In a method for monitoring layout changes for semiconductor chips, a first group of error data is generated by comparing a first layout with wiring and layout rules. A second group of error data is generated by comparing a second layout with the wiring and layout rules, the second layout being generated from layout changes of the first layout. The first group of error data is compared to the second group of error data and only error data that are different in the first and second groups is output for evaluation.
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Baenisch Andreas
Mueller Uwe
Obermaier Werner
Infineon - Technologies AG
Kik Phallaka
Sandoval Patrick
Slater & Matsil L.L.P.
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