Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-01-20
2002-05-14
Nguyen, Ha Tran (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000, C438S633000, C438S634000, C438S637000, C438S645000, C438S735000, C438S738000
Reexamination Certificate
active
06387797
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to manufacturing semiconductors and more specifically to a manufacturing method for forming semiconductors with reduced capacitance between interconnects.
BACKGROUND ART
As technology pushes towards deep sub-micrometer applications, the interconnects which connect integrated circuit devices formed in semiconductor substrates are getting closer together. In order to enhance the speed performance of these deep sub-micrometer devices, it is important to reduce the capacitance between the interconnects to reduce cross talk. Lower dielectric constant materials are required to reduce the capacitance. Air or vacuum has the lowest dielectric constant (approximately equal to 1) as compared to other common available dielectric materials such as silicon dioxide. To enhance the speed performance and reduce cross talk, some technologists have proposed forming voids in the dielectric between interconnects to reduce the dielectric constant.
A significant problem associated with the conventional method of forming voids in the dielectric between interconnects is the potential shorts between interconnects. As interconnects and space dimensions shrink, a small misalignment commonly found in a typical semiconductor process may cause the via openings formed above the interconnects to be extended through the dielectric to the voids. Subsequent filling of the via openings with a conductive material such as tungsten to form vias may cause the conductive material to partially or completely fill the voids. Since the spacings between interconnects are getting very small, any additional conductive material formed in the voids between interconnects could lead to shorts between the interconnects. A method for forming voids in dielectric between interconnects to reduce the capacitance between the interconnects and yet without the potential short circuit problem has long been sought but has eluded those skilled in the art.
DISCLOSURE OF THE INVENTION
The present invention provides a method of manufacturing semiconductors having reduced capacitance between interconnects.
The present invention further provides a method of manufacturing semiconductors that avoids metal deposition in voids formed in dielectric between interconnects.
The present invention still further provides a method of manufacturing semiconductors which avoid metal deposition in voids formed in dielectric between interconnects by providing an etch stop recess portion to prevent via openings from extending to the voids during the etching of the via openings.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5001079 (1991-03-01), Van Laarhoven et al.
patent: 5306947 (1994-04-01), Adachi et al.
patent: 5641712 (1997-06-01), Grivna et al.
patent: 5665657 (1997-09-01), Lee
patent: 5837618 (1998-11-01), Avanzino et al.
patent: 5969409 (1999-10-01), Lin
patent: 5981379 (1999-11-01), Tsai
patent: 6033981 (2000-03-01), Lee et al.
patent: 6069069 (2000-05-01), Chooi et al.
patent: 6077767 (2000-06-01), Hwang
patent: 0860 869 (1998-08-01), None
PCT International Search Report for counterpart PCT application serial No. PCT/US00/01429 filed Jan. 20, 2000.
Annapragada Rao
Bothra Subhas
Nguyen Ha Tran
Philips Electronics No. America Corp.
Zawilski Peter
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