Method for reducing switching noise in a programmable logic devi

Details Method for reducing switching noise in a programmable logic devi Method for reducing switching noise in a programmable logic devi

1997-08-08

1999-09-14

Tokar, Michael

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 39, H03K 19177

Patent

active

059528460

ABSTRACT:
A method for programming PLDs in which feedback signals are alternately programmed to produce counteractive switching signals in the interconnect matrix to reduce the coupling effect caused by multiple concurrent switching events. The method is applied to CPLDs having interconnect matrices including input lines and output lines connected by programmable connection circuits, and having macrocells connected at their output to one of the input lines via first selective inversion circuits, and connected at their input to the output lines via second selective inversion circuits. The method includes selecting a first macrocell generating a feedback signal which is routed to a second macrocell, generating a random command to either invert or not-invert the feedback signal, and, if the generated random command is to invert the feedback signal, programming the associated first selective inversion circuit to invert the feedback signal as it enters the interconnect matrix, and programming the associated second selective signal inversion circuit to re-invert the inverted feedback signal transmitted from the interconnect matrix to the second macrocell.

REFERENCES:
patent: 4903223 (1990-02-01), Norman et al.
patent: 5028821 (1991-07-01), Kaplinsky
patent: 5091661 (1992-02-01), Chiang
patent: 5530378 (1996-06-01), Kucharewski et al.
patent: 5617041 (1997-04-01), Lee et al.
Xilinx Programmable Gate Array Data Book, 1996, pp. 3-3 to 3-16, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124., No Month .

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