Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1997-11-07
1999-03-30
Quach, T. N.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438647, 438648, 438656, 438669, H01L 2128, H01L 21302
Patent
active
058888942
ABSTRACT:
A method for reducing stray conductive material near vertical surfaces in semiconductor manufacturing processes comprising the following steps. Deposit the gate oxide, polysilicon and cap oxide layers. Apply a Poly1A mask. The Poly1A mask pattern comprises the Poly1 areas that are part of the final circuit layout as well as additional Poly1 areas that are included to provide planar surfaces to prevent stringer formation. Etch the cap, polysilicon and gate oxide layers to partially form the transistor gate structures. Form oxide spacers on the sides of the transistor gate structures. Apply a source/drain mask. Deposit source/drain dopants to form diffusions. Deposit an interlayer dielectric. Mask and pattern contacts to the diffusions and the Poly1 layer. Deposit blanket TiN/Ti layer(s). Pattern the TiN/Ti layer(s) using a TiN/Ti mask and a dry anisotropic etch. Patterning the TiN/Ti layer(s) may create TiN/Ti stringers along vertical surfaces of the interconnect layer. However, by defining the Poly1A mask pattern to leave Poly1 in pre-defined potential stringer problem areas, these surfaces remain planar and thus free of stringers. Next, apply a Poly1B mask. The Polyl1B mask is defined such that the final Poly1 pattern is the logical AND of the Poly1A mask pattern and the inverse of the Poly1B mask. Then etch the cap, polysilicon and gate oxide layers to complete formation of the transistor gate structures.
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Chang Kai-Ning
Kong Weiran
Integrated Silicon Solution Inc.
Quach T. N.
Williams Gary S.
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