Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-11-14
2004-03-30
Baderman, Scott (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
Reexamination Certificate
active
06715105
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains generally to testing of digital electronic systems, and more particularly to a method for reducing stored patterns for integrated circuit test by embedding built-in-self-test circuitry for chip logic into a scan test access port.
BACKGROUND OF THE INVENTION
As the complexity of integrated circuits (ICs) increases, so does the cost of testing the circuits during process and manufacture. As a result, integrated circuit chips are increasingly designed using a process commonly referred to as Design For Testability (DFT). Under the DFT model, integrated circuits are designed to include on-chip testing hardware to allow manufacturing testers to apply external tests to the chip and/or to allow internal tests to execute within the chip to verify the proper functionality of the chip. The goal is to balance the amount of the on-chip testing hardware with the costs of external test equipment and the amount of time and cost required to generate effective tests and detect or isolate faults such that the overall costs due to the additional on-chip testing hardware is reduced.
One well-known DFT technique is called scan testing. Scan testing requires the use of a set of scan registers, each of which possesses both serial- and parallel-load capability. In a typical scan test, a set of scan registers is connected in series. Such a set of serially connected scan registers is referred to herein as a scan path. Input data is loaded serially (“shifted”) into each of the scan registers via a Test Access Port (TAP). Once the input data is loaded, the contents of the scan registers are driven into the circuit under test (CUT) in parallel and the CUT is instructed to execute one or more clock cycles. The output of the CUT after execution of the one or more clock cycles is then captured in parallel into the scan registers and shifted serially out under control of the TAP.
One form of scan testing is known as boundary scan. In boundary scan, each of the scan registers is coupled between an I/O pin of the CUT and circuitry internal to the CUT. During a boundary scan test, the scan registers therefore replace the I/O pins of the IC for loading and receiving data.
Scan testing is advantageous for several reasons. First, scan test allows a high degree of controllability and observability of signals inside the chip. Any set of data inputs can be shifted into a given scan path and applied to the CUT, and the CUT may be allowed to execute for any controlled number of clock cycles before the output is observed. Scan paths may be fully integrated (meaning that a scan register is substituted for each functional register in a given data path) or isolated (meaning that the scan register is not in the normal data path). This gives the designer of the IC flexibility in determining which portions of the CUT warrant special on-chip testing hardware. In addition, because the scan registers are loaded via a serial TAP, test data can be input to the CUT via a single serial data line rather than by applying a tester channel (e.g., a bed-of-nails tester) to each I/O pin or test node of the CUT. This significantly reduces tester configuration and setup costs and ensures that no pin-to-pin data interference occurs.
As just described, scan testing requires the use of a TAP and a serial communications protocol for controlling the shifting in of test stimulus, test execution, and shifting out of test response data. The TAP architecture and TAP communications protocol has been standardized in the well-known IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture [IEEE 1989].
FIG. 1
is a block diagram of the chip architecture for the IEEE 1149.1 standard. As shown, a chip (or board)
10
implemented according to the standard includes coupled via a plurality of scan cells
50
a
,
50
b
, . . .
50
p
coupled between chip specific application logic
74
a
-
74
d
(interconnections not shown) and a plurality of input and/or output (I/O) pads
52
a
,
52
b
, . . . ,
52
p
. Chip
10
includes a TAP circuit block
20
having a test data in (TDI) port
22
, a test mode select (TMS) port
24
, a test clock (TCK) port
26
, and a test data out (TDO) port
28
. TAP circuit block
20
includes an instruction register
32
, a bypass register
34
, and optionally one or more miscellaneous registers
36
, each coupled between the TDI input and the input of a multiplexer
38
. Boundary scan cells
50
a
,
50
b
, . . .
50
p
are connected in series between the test data in TDI input and an input of multiplexer
38
. TAP circuit block
20
also includes a scan-in port S
i
80
and one or more scan-out port S
o
82
, discussed hereinafter. Scan-in port
80
is coupled to the TDI port
22
; scan-out port(s)
82
are coupled to an input of multiplexer
38
. Multiplexer
38
is programmable to select one of its inputs, including the instruction register
32
, the bypass register
34
, one of the miscellaneous registers
36
, (one of) the scan-out port(s)
82
, or the output of the boundary scan chain
50
(i.e., the contents of scan cell
50
p
), for output onto the TDO port
28
. TMS port
24
and TCK port
26
are coupled to a TAP controller
30
(which implements a finite state machine FSM
31
). The current state of the TMS signal, in combination with its past states, determines the operation of the TAP
20
. Test clock signal TCK is used to synchronize input of the mode select signal TMS and test data in signal TDI into the TAP. Test mode select signal TMS controls the finite state machine implemented in the TAP controller
30
which controls whether the TAP
20
accepts test data or instructions.
Scan testing is not limited to boundary scan (implemented in
FIG. 1
by scan path
50
), where the scan path includes scan cells only at the I/O pins. Scan paths may be implemented anywhere on the chip where a set of data storage cells exist. Since integrated circuits are often implemented modularly (i.e., where the integrated circuit functions are divided into a set of separate logic blocks) multiple internal scan paths may be implemented around each logic block to test each logic block independently of the other logic blocks.
FIG. 1
illustrates the implementation of multiple internal scan paths
72
a
,
72
b
,
72
c
, and
72
d
. Each scan path implements a set of interconnected scan cells (not shown) corresponding to a set of data storage cells in a respective logic block
74
a
-
74
d
. Since each logic block is independent of the others, the number of scan cells in each scan path
72
a
,
72
b
,
72
c
,
72
d
may vary. Also, since each scan path
72
a
,
72
b
,
72
c
,
72
d
is independent of the others, a single scan-in input S
i
80
may be fed into each scan path without affecting the randomness of the test pattern suite applied to any given scan path. During a scan test, the TAP shifts data in from the TDI port
22
along the scan-in S
i
80
path and into each scanpath[0 . . . n]
72
a
,
72
b
,
72
c
,
72
d
. The number of bits shifted into the scan paths
72
a
-
72
b
via the scan-in port S
i
80
is equivalent to the number of scan cells in the longest scan path
72
a
,
72
b
,
72
c
, or
72
d
. Alternatively, each scan path can be loaded one at a time with exactly the number of bits in that scan chain.
In operation, an instruction is clocked in serially from the TDI port
22
into instruction register
32
. Test controller
30
responds to the instruction by configuring the test circuitry according to the instruction (e.g., selecting the input of the scan cells to come from their serial inputs via the scan chain rather than their parallel inputs via the I/O pads, or selecting the multiplexer
38
input). Each instruction enables a single serial test data register path between TDI and TDO. The instruction is then executed under the control of the TAP controller
30
(e.g., shifting data serially into or out of the scan cells in synchronization with the test clock TCK signal).
Another well-known manufacturing testing technique is called Built-In-S
Agilent Technologie,s Inc.
Baderman Scott
Damiano Anne L.
LandOfFree
Method for reducing stored patterns for IC test by embedding... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for reducing stored patterns for IC test by embedding..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for reducing stored patterns for IC test by embedding... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3264080