Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-10-30
2007-10-30
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
10710420
ABSTRACT:
A method for reducing standard delay format (SDF) file size is disclosed. The state-dependent descriptions in cell descriptions of the SDF file, which are not intended to be used, are removed by referring to a design description of an integrated circuit design. Therefore, the SDF file size is reduced and the simulation result generated by a simulator is not affected with the reduced SDF file.
REFERENCES:
patent: 6857110 (2005-02-01), Rupp et al.
patent: 2003/0125917 (2003-07-01), Rich et al.
Huang Chien-Ming
Wu Kun-Cheng
Chiang Jack
Faraday Technology Corp.
Memula Suresh
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