Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-06-15
2003-06-17
Philogene, Haissa (Department: 2821)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06581194
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and/or apparatus for verification of integrated circuit (IC) designs generally and, more particularly, to a method and/or apparatus for reducing simulation overhead for external models.
BACKGROUND OF THE INVENTION
Conventional integrated circuit (IC) model applications are written in simulator languages and can implement third party tools requiring additional third party extension languages. IC models are typically built in one of three languages. The first language may be a proprietary simulator language. The proprietary simulator language allows designers to clearly understand the IC model and perform modifications, if necessary. However, such proprietary simulator languages have limited capabilities and require increased coding when compared to the third party extension languages, causing simulation slow down. Writing IC models in proprietary simulator language is inefficient, since the simulator languages do not allow for re-entrant tasks, (i.e., no reusability of code is provided). Furthermore, hardware design languages are geared toward designing hardware, not test bench models.
The second language is the C/C++ language. The third language is the third party simulator extension language. The C/C++ language and the third party extension language allow IC modeling to be accomplished with current software standards and provide increased reusability. However, C/C++ and third party extension languages require the IC model to communicate with the simulator through an interface. The interface significantly slows down the entire simulation process. Moreover, as the complexity of IC models increases, communication with the simulator increases, greatly reducing the throughput of the simulator.
Some conventional IC design simulators have attempted to speed up or accelerate simulation through other languages. However, IC model interfacing with the simulator remains slow and interfacing with the simulator is not reduced.
SUMMARY OF THE INVENTION
The present invention concerns a method for simulating verification of an IC design. The method generally comprises the steps of (A) generating one or more transactions of a simulation and (B) testing the one or more transactions and possibly generating an exception. The exception may be configured to initiate a modification of step (A).
The objects, features and advantages of the present invention include providing a method and/or apparatus for reducing simulation overhead for integrated circuit (IC) models that may (i) allow a checker and a transaction generator to be simultaneously built, (ii) allow the checker to become integrated into the IC design, and/or (iii) allow the speed of the simulation to be directly dependent upon the simulator.
REFERENCES:
patent: 5594741 (1997-01-01), Kinzelman et al.
patent: 6163763 (2000-12-01), Cox et al.
patent: 6182258 (2001-01-01), Hollander
Carpenter David W.
Richards Jana L.
LSI Logic Corporation
Philogene Haissa
Tran Thuy Vinh
LandOfFree
Method for reducing simulation overhead for external models does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for reducing simulation overhead for external models, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for reducing simulation overhead for external models will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3086913