Method for reducing power consumption through dynamic memory...

Details Method for reducing power consumption through dynamic memory... Method for reducing power consumption through dynamic memory...

2001-03-15

2003-10-14

Nguyen, Hiep T. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C713S320000

Reexamination Certificate

active

06633951

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to mobile computing systems, and more specifically to a method for reducing power consumption of the same.
BACKGROUND OF THE INVENTION
The emphasis in mobile computing system (MCS) design is to reduce size and weight while increasing operating frequencies. One way in which MCSs have been reduced in size and weight is through a reduction in battery size. Today, MCSs may operate at frequencies of 850 MHz or more and these higher frequencies require more power. Therefore the emphasis on size reduction and increased performance has led to an emphasis on power conservation.
Most personal computers including MCSs use dynamic random access memory (DRAM) as main memory due to the DRAM's low cost per bit and low power consumption. A typical DRAM storage cell is shown in FIG.
1
. The basic memory storage cell
100
, shown in
FIG. 1
, is a capacitor, that is, an integrated capacitor
105
connected in series with a control transistor
110
. The control transistor
110
acts as an on-off switch. To store data in, or read data from, the memory cell, the control transistor
110
is turned on, by applying a positive pulse to control line (word line)
115
. When the control transistor
110
is turned off, the integrated capacitor
105
is isolated from the rest of the circuitry. The state of memory storage cell
100
is retained in the charge on integrated capacitor
105
. When the integrated capacitor
105
is charged, a binary 1 is stored. When the integrated capacitor
105
is discharged, a binary 0 is stored. To read data from memory storage cell
100
the control transistor
110
is turned on connecting the integrated capacitor
105
to sense line (bit line)
120
. External circuitry examines the state of integrated capacitor
105
and informs the central processing unit (CPU).
The capacitance in a memory storage cell is very small and therefore, any charge on it will quickly leak off. This would alter the state of the memory storage cell and the stored data would be lost. To avoid lost data, the charge on the cell is periodically refreshed. Typically the memory storage cell is refreshed approximately every two milliseconds. This refreshing process consumes power that, as a percentage of total power consumption, becomes significant in a MCS during some modes of operation.


REFERENCES:
patent: 3568162 (1971-03-01), Toy
patent: 3805254 (1974-04-01), Schuur
patent: 4106105 (1978-08-01), Pross, Jr.
patent: 6345333 (2002-02-01), Sassa et al.

Affiliated with

Also associated with

Rating

Method for reducing power consumption through dynamic memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for reducing power consumption through dynamic memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for reducing power consumption through dynamic memory... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3170288