Method for reducing pitch

Details Method for reducing pitch Method for reducing pitch

2002-06-12

2004-08-10

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S758000

Reexamination Certificate

active

06774051

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor fabrication methods, and more particularly to methods for reducing spacing dimensions or pitch between conductive features.
2. Description of Related Art
Integrated circuits are currently in widespread use in nearly all types of electronic equipment, ranging from household goods and appliances to computer networking and sophisticated supercomputers. Electronic devices such as resistors, capacitors, transistors, etc., are typically fabricated on semiconductor wafers (e.g., silicon wafers) using photolithographic processes. Such photolithographic processes commonly involve the formation of various layers of desired materials via oxidation or deposition operations, the patterning of layers via removal operations such as wet etches, reactive ion etches, etc., and material modification operations such as doping operations and heat treatments.
A common objective among photolithographic techniques is to reduce or control critical dimensions of features, while maintaining precision. For instance, the dimensional spacing or pitch between adjacent devices, required for device isolation to avoid short circuit conditions and signal cross talk, can contribute significantly to increases in overall dimensions of integrated circuits. Thus, as integrated circuits become smaller and denser, the need to reduce spacing dimensions or pitch, becomes increasingly important.
Limits on minimum device spacing typically stem from limits inherent in the photolithographic process itself. In the prior art, devices are generally arranged as close to one another as the limits of the photolithographic processes will permit. The number and order of operations in a given photolithographic process may also affect the resulting spacing of circuit devices on semiconductor wafers. An ongoing need exists to reduce the size of integrated circuits by reducing the spacing dimensions or pitches between adjacent devices fabricated on semiconductor wafers via photolithographic processes.
SUMMARY OF THE INVENTION
A method is disclosed for forming a semiconductor structure with conductive features having reduced dimensional spacings or pitch. In one embodiment, a substrate having a conductive layer formed thereon is provided. A first or cap dielectric layer is formed on the conductive layer. At least one, and preferably multiple, photoresist features are formed on the first dielectric layer. First polymer layers are formed over exposed surfaces of each of the photoresist features. The first polymer layers are used to pattern the first dielectric layer and the conductive layer, thereby forming a plurality of first dielectric and conductive features. The plurality of first dielectric and conductive features may comprise: (a) at least one dielectric feature and a plurality of conductive features; (b) a plurality of dielectric features and at least one conductive feature; or (c) a plurality of dielectric features and a plurality of conductive features.
The first polymer layers and the photoresist features are removed. Subsequently, a second dielectric layer is formed over and about the dielectric features and portions of the underlying conductive features. An upper portion of the second dielectric layer is removed such that an upper surface of the second dielectric layer is substantially even with (i.e., flush with) upper surfaces of the first dielectric features. The first dielectric features are then removed, whereby the second dielectric layer is thus formed into second dielectric features.
A second polymer layer is formed over remaining portions of the second dielectric layer (i.e., the second dielectric features), and over portions of an upper surface of each of the conductive features adjacent to corresponding remaining portions of the second dielectric layer. The second polymer layers are used to pattern the conductive features, thereby removing for example central portions of each of the conductive features and producing second conductive features. The second polymer layers and the remaining portions of the second dielectric layer are subsequently removed.
The resulting semiconductor structure includes the substrate and a number of second conductive features, which may be for example twice the original number of conductive features. The second conductive features have reduced dimensional spacing or pitch with regard to the original conductive features.
Any feature or combination of features described herein are included within the scope of the present invention provided that the features included in any such combination are not mutually inconsistent as will be apparent from the context, this specification, and the knowledge of one of ordinary skill in the art. Additional advantages and aspects of the present invention are apparent in the following detailed description and claims.


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patent: 6337264 (2002-01-01), Bhakta
patent: 6399483 (2002-06-01), Liu et al.
patent: 6458385 (2002-10-01), Jamiolkowski et al.
patent: 6475892 (2002-11-01), Bhakta
patent: 6548385 (2003-04-01), Lai
patent: 2003/0082916 (2003-05-01), Chung et al.

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