Method for reducing pin overhead in non-scan design for...

Details Method for reducing pin overhead in non-scan design for... Method for reducing pin overhead in non-scan design for...

2006-05-23

2006-05-23

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07051302

ABSTRACT:
A method and apparatus for reducing pin overhead in a non-scan design for testability, The method comprises connecting control signals of test points l1£l2£, . . . , £lhto a first primary input PI1through AND gate switch, connecting control signals of test points lj, . . . , £lqto a kth primary input PIkthrough AND gate switch until every test point is connected to one of the primary inputs PI1, PI2, . . . , PIk, connecting a 1-control point to AND gate directly, connecting a 0-control point to AND gate through inverter, sharing one AND gate among all control points that are connected to the same primary input, controlling all control points by an uniform test signal, and checking whether the test points and the primary inputs produce new re-convergent fan-out while reducing inputs of the control signals.

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