Method for reducing pin counts and microprocessor using the...

Details Method for reducing pin counts and microprocessor using the... Method for reducing pin counts and microprocessor using the...

2009-03-30

2011-12-20

Portka, Gary (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Address multiplexing or address bus manipulation

C365S230020

Reexamination Certificate

active

08082417

ABSTRACT:
The present invention relates to a microprocessor with reduced pin counts. The microprocessor transmits a higher bit address, a lower bit address and data via a common port so that a pin for transmitting the higher bit address is omitted. In an embodiment of the present invention, a new higher bit address latching signal is added in order to latch the higher bit address so that an original lower bit address latching signal and the higher bit address latching signal can respectively latch the lower bit address and the higher bit address.

REFERENCES:
patent: 4839856 (1989-06-01), Tanaka
patent: 5524228 (1996-06-01), Maruyama et al.
patent: 6564285 (2003-05-01), Mills et al.
patent: 6778463 (2004-08-01), Chen
patent: 6895465 (2005-05-01), Hashimoto et al.
patent: 2006/0129701 (2006-06-01), Qawami et al.

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