Adhesive bonding and miscellaneous chemical manufacture – Delaminating processes adapted for specified product – Delaminating in preparation for post processing recycling step
Patent
1978-12-26
1980-09-16
Massie, Jerome W.
Adhesive bonding and miscellaneous chemical manufacture
Delaminating processes adapted for specified product
Delaminating in preparation for post processing recycling step
29571, 29578, 29580, 148187, 148188, 156656, 156657, 156662, 156668, 1566591, 430313, H01L 21225, H01L 21308
Patent
active
042228166
ABSTRACT:
A method for reducing parasitic capacitance in semiconductor devices, particularly for the removal of raised portions of conductive layers overlying and capable of being capacitively coupled to other conductors in semiconductor memory integrated circuits. The method provides for the application of a masking or photoresist layer over the surface of a substrate containing portions of a conductor to be removed such that the masking layer completely covers the conductor. Next a uniform thickness of the masking layer is removed to expose only the raised portions of the conductor which are subsequently selectively etched through the remainder of the masking layer. Application of the method to a manufacturing process for a dynamic MOSFET memory array is also described in which bit sense line capacitance is substantially reduced.
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Kruggel et al., "Low Capacitance Semiconductor . . . Profile," IBM Technical Disclosure Bulletin, vol. 17, No. 1, (6/74), p. 18.
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Noble, Jr. Wendell P.
Unis Richard A.
International Business Machines - Corporation
Massie Jerome W.
Walter, Jr. Howard J.
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