Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2011-06-21
2011-06-21
Bragdon, Reginald G (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711SE12026
Reexamination Certificate
active
07966456
ABSTRACT:
Disclosed is a method for reducing number of writes in a write-back non-volatile cache memory. The method comprises: writing a plurality of data in the cache memory, wherein cache lines meta data for each of the plurality of data is marked as dirty; determining a set of data of the plurality of the data in the cache memory to be flushed to a hard disk, wherein the hard disk is operatively coupled to the cache memory; flushing the set of data of the plurality of data to the hard disk from the cache memory; and writing a clean-marker to the cache memory specifying which of the plurality of the data has been flushed to the disk.
REFERENCES:
patent: 5448719 (1995-09-01), Schultz et al.
patent: 2006/0047888 (2006-03-01), Nishihara et al.
Mangold Rick
Trika Sanjeev N.
Vogan Andrew
Ahmed Hamdy S
Bragdon Reginald G
Grossman Tucker Perreault & Pfleger PLLC
Intel Corporation
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