Method for reducing number of bits used in storage of instructio

Details Method for reducing number of bits used in storage of instructio Method for reducing number of bits used in storage of instructio

1998-10-06

2000-10-31

Ellis, Richard L.

Electrical computers and digital processing systems: memory

Address formation

Combining two or more values to create address

711218, 712205, G06F 1206

Patent

active

061417424

ABSTRACT:
Variable-length instructions are prepared for simultaneous decoding and execution of a plurality of instructions in parallel by reading multiple variable-length instructions from an instruction source and determining the starting point of each instruction so that multiple instructions are presented to a decoder simultaneously for decoding in parallel. Immediately upon accessing the multiple variable-length instructions from an instruction memory, a predecoder derives predecode information for each byte of the variable-length instructions by determining an instruction length indication for that byte, assuming each byte to be an opcode byte since the actual opcode byte is not identified. The predecoder associates an instruction length to each instruction byte. The instructions and predecode information are applied to an instruction buffer circuit in a memory-aligned format. The instruction buffer circuit prepares the variable-length instructions for decoding by converting the instruction alignment from a memory alignment to an instruction alignment on the basis of the instruction length indication. The instruction buffer circuit also assists the preparation of variable-length instructions for decoding of multiple instructions in parallel by facilitating a conversion of the instruction length indication to an instruction pointer.

REFERENCES:
patent: 3731283 (1973-05-01), Carlson et al.
patent: 5386534 (1995-01-01), Sibigtroth et al.
patent: 5659700 (1997-08-01), Chen et al.
patent: 5835973 (1998-10-01), Kyuma et al.

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