Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Recessed oxide by localized oxidation
Reexamination Certificate
2000-03-03
2002-03-05
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Recessed oxide by localized oxidation
C438S297000
Reexamination Certificate
active
06352908
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method of forming an isolation region in a semiconductor device, and more specifically to a method of reducing nitride residue in a LOCOS isolation area.
2. Description of the Prior Art
As semiconductor device dimensions are decreased, and device density increases, it becomes more difficult to efficiently and reliably fabricate isolation structures for separating active areas of the device. One common method of forming isolation structures for semiconductor devices is referred to as local oxidation process (LOCOS isolation process). The area formed via such a process is referred to as LOCOS isolation area.
FIGS. 1A through 1E
illustrate cross-sectional views of an integrated circuit as formed during sequential steps of a prior art LOCOS based method of forming a field oxide isolation region. Referring to
FIG. 1A
, a silicon substrate
12
having a top surface and a bottom surface is provided. An upper pad oxide layer
14
is formed superjacent the top surface of the substrate
12
, and a lower pad oxide layer
15
is formed subjacent the bottom surface of the substrate
12
. An upper pad silicon nitride layer
16
is formed superjacent the upper pad oxide layer
14
, and a lower pad silicon nitride layer
18
is formed subjacent the lower pad oxide layer
15
. The upper and lower pad oxide layers
14
and
15
are used to provide improved adhesion between the substrate
12
and the upper and lower pad silicon nitride layers
16
and
18
respectively. Next, forming a photo resistive mask over the upper pad silicon nitride layer
16
, the mask defining an intended active area
20
. A lithography process is performed to remove a portion of the upper pad silicon nitride layer
16
thereby exposing a portion of the upper pad oxide layer
14
including the intended active area
20
.
Referring to
FIG. 1B
, the upper surface of the integrated circuit is subjected to an etching solution, such as a hydrofluoric acid solution (HF), to remove the exposed portion of the upper pad oxide layer
14
thereby exposing a portion of the upper surface of the substrate
12
, and forming an undercut cavity
26
by removing a portion of the upper pad oxide layer
14
under the exposed edges of the remaining portion of the upper pad silicon nitride layer
16
Referring to
FIG. 1C
, an oxide layer, or etching stop layer,
32
is formed on the exposed portion of the upper surface of the substrate
12
and in the cavities
26
. The etching stop layer
32
is typically formed in accordance with a thermal oxidation process. During the thermal oxidation process for forming the etching stop layer
32
, an upper thin oxide layer
34
is incidentally formed superjacent the remaining portion of the upper pad silicon nitride layer
16
, and a lower thin oxide layer
35
is incidentally formed subjacent the lower pad silicon nitride layer
18
. The incidental formation of the upper and lower thin oxide layers
34
and
35
occurs because the ratio of the oxidation rate of silicon to the oxidation rate of silicon nitride is approximately 25:1. Therefore, during the thermal oxidation process to form several Angstroms of the etching stop layer
32
, oxidation also occurs on the surfaces of the remaining portion of the upper pad silicon nitride layer
16
and the surfaces of the lower pad silicon nitride layer
18
thereby forming the upper and lower thin oxide layers
34
and
35
. The thin oxide layers
34
and
35
are typically formed to have a thickness which ranges between several Angstroms and tens of Angstroms, that is between approximately 1 and 100 Angstroms.
Referring to
FIG. 1D
, a low pressure chemical vapor deposition (LPCVD) process is performed to deposit: a lower silicon nitride layer
42
subjacent the lower thin oxide layer
35
; and an upper silicon nitride layer (not shown) superjacent the remaining portion of the upper pad silicon nitride layer
16
and superjacent the etching stop layer
32
. Subsequently, a anisotropic etching process is performed on the upper silicon nitride layer to form silicon nitride spacers
44
adjacent the thin oxide layers
34
coated on the sidewalls of the remaining portion of the upper pad silicon nitride layer
16
.
Referring to
FIG. 1E
, the remaining portion of the upper silicon nitride layer
16
and silicon nitride spacers
45
are used as a mask during an oxidation process to form a field oxide area
52
. Subsequent steps of the prior art LOCOS based method of forming a field oxide isolation region include: removing the silicon nitride spacers
44
, the remaining portion of the upper pad silicon nitride layer
16
, the remaining portion of the upper pad oxide layer
14
, and the lower silicon nitride layer
42
; as well as forming and removing a sacrificial layer (not shown) to define an active area.
There are several problems associated with the prior art LOCOS based method of forming a field oxide isolation area. The thin oxide layers
34
and
35
, which have a thickness of several Angstroms, cause problems in subsequent removal steps including removing the silicon nitride spacers
44
, the remaining portion of the upper pad silicon nitride layer
16
, and the remaining portion of the upper pad oxide layer
14
. Conventionally, silicon nitride can be removed by applying a high temperature phosphoric acid solution. However, the phosphoric acid solution has a high selectivity in removing silicon nitride and oxide (the ratio is typically 40:1), and so the thin oxide layers
34
and
35
are not removed as quickly as the silicon nitride layers. Therefore the lower thin oxide layer
35
, which forms a barrier between the lower pad silicon nitride layer
18
and the silicon nitride layer
42
, impedes removal of the lower pad silicon nitride layer
18
. Because the silicon nitride layer
42
cannot be efficiently removed by application of the phosphoric acid solution, a silicon nitride residue remains after the subsequent removal steps. Also, the required period of time of applying the phosphoric acid solution to remove the silicon nitride is long which can cause manufacturing delays. Furthermore, the silicon nitride residue causes photo leveling issues in etching speed drifting.
What is needed is an improved LOCOS based method of forming a field oxide isolation region wherein silicon nitride residue is substantially eliminated.
What is also needed is an improved LOCOS based method of forming a field oxide isolation region wherein it is not necessary to apply phosphoric acid solution for an excessive amount of time during steps of removing silicon nitride.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an improved LOCOS based method of forming a field oxide isolation region wherein silicon nitride residue is substantially eliminated.
It is another object of the present invention to provide an improved LOCOS based method of forming a field oxide isolation region wherein it is not necessary to apply phosphoric acid solution for an excessive amount of time during steps of removing silicon nitride.
Briefly, a presently preferred embodiment of the present invention provides an improved method of forming an isolation structure including the steps of: providing a silicon substrate having a top surface and a bottom surface; forming an upper pad oxide layer superjacent the top surface of the substrate, and a lower pad oxide layer subjacent the bottom surface of the substrate; forming a nitride masking layer superjacent the upper pad oxide layer, and a lower pad silicon nitride layer subjacent the lower pad oxide layer; patterning and etching the nitride masking layer to expose a portion of the upper pad oxide layer; applying a first etching solution to the exposed portion of the upper pad oxide layer to expose a portion of the substrate substantially defining the boundaries of an active area; performing an oxidation process to form an etching stop layer over the exposed portion of the substrate, the oxidation process also forming an uppe
King Wei-Sheng
Wang Tso-Chun Tony
Chou Chien-Wei (Chris)
Mosel Vitelic Inc.
Niebling John F.
Oppenheimer Wolff & Donnelly LLP
Pompey Ron
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