Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
2000-04-26
2002-04-16
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S676000, C438S123000
Reexamination Certificate
active
06373126
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor packaging, and more particularly, to a package of a semiconductor device having increased ability to limit moisture flow through the packaging material and into the area of the die and die pad
2. Discussion of the Related Art
Reference is made to
FIGS. 1-3
, wherein a typical packaged semiconductor structure
10
is shown. As is well known, a die pad
12
has a die
14
epoxied thereon and tie bars
16
,
18
extending therefrom. Bonding wires
20
connect the die
14
to the inner ends of leads
22
. The die pad
12
, die
14
, wire bonding
20
and inner ends of the leads
22
are packaged in epoxy
24
, commonly referred to as plastic packaging, with the outer ends of the leads
22
extending from the epoxy
24
. These leads
22
may be plugged into a printed circuit board
26
, as shown in FIG.
3
.
Over a period of time, moisture
28
diffuses through the plastic package
24
and into the area of the die
14
, die pad
12
, and wire bonding
20
. Through the operation of the device
10
, heat buildup can cause moisture in those critical areas to vaporize, creating large amounts of steam pressure in pockets adjacent to these critical areas. In the case of moisture near the lower side of the die pad
12
, blisters may form of sufficiently large size to cause connection problems between the printed circuit board
26
and the device
10
. In the case of moisture near the upper side of the die
14
, wire bond failure, die face damage, and/or die fracture can occur. Obviously, situations where such delaminations can occur are highly undesirable and can result in severe reliability problems.
Current practice is to measure how well each packaged device performs under JEDEC stress testing (specified temperature and humidity environment for a specified time for each Level). Manufacturers of semiconductor devices strive to reach Level 1 as that is the only level for which neither device baking nor a hermetic bagging are required. This “bake and bag”process involves additional expense, and would not be necessary if the package were inherently resistant to moisture flow therethrough to the area of the die
14
, die pad
12
and wire bonding
20
.
FIG. 4
shows a packaged semiconductor device
29
which utilizes an anodized aluminum heat spreader
30
in contact with the die pad
32
for dissipation of heat buildup during the operation of the device
29
. In the fabrication of the device
29
, the heat spreader
30
is placed in the well of a transfer molding machine, legs
34
extending from the heat spreader
30
contacting the bottom of the well, and a lead frame
36
having a die
38
associated therewith and wire bonded thereto is placed over the heat spreader
30
with the die pad
32
in contact with the heat spreader
30
, so as to be an interference fit with the heat spreader
30
. As molding compound
40
is forced into the area of the die
38
and die pad
32
, air can be trapped above the heat spreader
30
and beneath the die pad
32
to form an air void therebetween. The heat spreader
30
includes apertures
42
therethrough to allow this air void to pass through the apertures
42
and away from the area of the die pad
32
, thereby relieving pressure from this area. While this configuration is effective for this purpose, the problem of limiting moisture ingress into the area of the die pad
32
, die
38
, and wire bonding is not addressed. Indeed, the apertures
42
in the heat spreader
30
will readily allow moisture therethrough directly into the area of the die pad
32
in contact with the heat spreader
30
. Furthermore, the problem of moisture ingress into the area of the die
38
and wire bonding through the packaging material thereabove is not addressed.
Therefore, it would be highly desirable to provide a system for limiting moisture diffusion through the plastic packaging material to the critical areas of the die, die pad, and wire bonding, so that the delamination problems described above are avoided.
SUMMARY OF THE INVENTION
In the present invention, in the environment of a semiconductor die epoxied to a die pad, with tie bars extending from the die pad, barrier structures are secured to the tie bars so as to have barrier bodies positioned on opposite sides of and overlying the die-die pad assembly. Each barrier body is spaced from the die-die pad assembly, and has a plurality of small apertures therethrough. As moisture diffuses through the plastic package material, the barrier bodies act as baffles to limit such diffusion in the direction of the die-die pad assembly to only that passing through the apertures. From these apertures the moisture diffuses in a spreading manner. Additional barrier structures may be provided which have barrier bodies overlying the above-described barrier bodies, the additional barrier bodies having apertures therethrough which are non-aligned with the apertures of the first-described barrier bodies to provide an even longer moisture flow path to the die-die pad area.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there are shown and described embodiments of this invention simply by way of the illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications and various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.
REFERENCES:
patent: 3585455 (1971-06-01), Naylor et al.
patent: 4589010 (1986-05-01), Tateno et al.
patent: 5162895 (1992-11-01), Takahashi et al.
patent: 5485037 (1996-01-01), Marrs
patent: 5714792 (1998-02-01), Przano
patent: 5889318 (1999-03-01), Corisis
patent: 5903048 (1999-05-01), Bandou et al.
Blish Richard C.
Patel Pramod
Clark Sheila V.
Winters Paul J.
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