Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2001-07-20
2003-04-15
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S593000, C438S952000, C438S974000
Reexamination Certificate
active
06548387
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for forming a semiconductor device, and more particularly to a method for reducing hole defects in the polysilicon layer.
2. Description of the Prior Art
Flash memory is the most potential memory in the semiconductor industry. Flash memory has been broadly applied to repeatedly access data and to remain assessable during power break down, such as the film of digital camera or the basic input-output system of a motherboard. Because flash memory has the advantages of electrically erasable and programmable mechanisms, it can simultaneously proceed the erase and the program mechanisms to all flash memory cells in the whole memory array. Accordingly, how to advance the performance and reduce the cost of the flash memory became an important subject.
Anti-reflective coatings have been used in the fabrication of small dimension integrated circuits (ICs) to provide better control over the photolithographic process. In particular, organic BARCs (bottom anti-reflective coatings) have been used during the contact hole masking step to reduce the reflections from the underlying topography substrate and thereby provide better control over the width of the photoresist mask openings which are used to form contact holes of a desired width.
Referring to
FIG. 1A
, firstly, a semiconductor substrate
100
is provided, and a polysilicon layer
102
is formed over a semiconductor substrate
100
. Then, a silicon oxide layer
104
is formed over the polysilicon layer
102
. A bottom anti-reflective coating (BARC) layer
106
is formed on the silicon oxide layer
104
by using spin-coating method, wherein the bottom anti-reflective coating (BARC) layer
106
has a micro bubbles
107
therein. A photoresist layer
108
is formed on the bottom anti-reflective coating (BARC) layer
106
by using spin-coting method. The photoresist layer
108
has an opening by using conventional lithographic technology.
Referring to
FIG. 1B
, the bottom anti-reflective coating (BARC) layer
106
, the silicon oxide layer
104
, and the polysilicon layer
102
are etched by using the photoresist layer
108
as a mask. Because the bottom anti-reflective coating (BARC) layer
106
has micro bubbles
107
therein, the active area interface between the substrate
100
and the polysilicon layer
102
has hole defects. Then, the photoresist layer
108
is removed.
For the forgoing reasons, a necessary method for reducing hole defects in the polysilicon layer is required. The solvent and bake treatment can reduce hole defects in the polysilicon layer.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method for reducing hole defects in the polysilicon layer that substantially can reduce hole defects in the polysilicon layer in conventional process.
One object of the present invention is to provide a method for reducing hole defects in the polysilicon layer to improve the hole defects issue.
In order to achieve the above object, the present invention provides a method for reducing hole defects in the polysilicon layer. The method at least includes the following steps. First of all, a semiconductor substrate is provided, a polysilicon layer is formed over the semiconductor substrate. Then, no hole defects bottom anti-reflective coating process is performed, wherein the no hole defects bottom anti-reflective coating process is selected from the group consisting of dehydration baking, hydrophobic solvent treatment, and steady baking. Finally, a bottom anti-reflective coating is formed over the polysilicon layer.
REFERENCES:
patent: 5312780 (1994-05-01), Nanda et al.
Hsu Chung-Jung
Huang Chih-Hsien
Booth Richard
United Microelectronics Corporation
LandOfFree
Method for reducing hole defects in the polysilicon layer does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for reducing hole defects in the polysilicon layer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for reducing hole defects in the polysilicon layer will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3001159