Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-04-01
2004-02-03
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S723000, C438S437000, C438S622000, C438S597000
Reexamination Certificate
active
06686279
ABSTRACT:
FIELD OF THE INVENTION
The present claimed invention relates to the field of semiconductor processing. More particularly, the present claimed invention relates to a method for forming vias.
BACKGROUND ART
As semiconductor geometries continue to become smaller and smaller, new difficulties arise in the fabrication of the correspondingly smaller features. As one example, when device sizes decrease in size (in order to form more devices on each wafer), features such as vias have critical dimensions (CDs) which become considerably smaller. The reduced CD of, for example, a via has certain drawbacks associated therewith. Referring now to Prior Art
FIG. 1A
, a side sectional view of a via having a reduced CD is shown. In Prior Art
FIG. 1A
, a substrate
100
has a via
102
formed therein. In the structure of Prior Art
FIG. 1A
, the critical dimension (CD) is shown as the width, W, of via
102
. Furthermore, it is important to note that the depth, D, of via
102
is much larger than the CD or width, W, of via
102
. Hence, via
102
is typically referred to as a high aspect ratio via.
Referring now to Prior Art
FIG. 1B
, as the CD of via
102
decreases, significant manufacturing difficulties arise. For example, landing of the via on an underlying target such as for example metal layer (M
2
)
106
, becomes increasingly difficult. That is, during the formation of via
102
, a portion
108
of via
102
“lands” on target
106
. As shown in Prior Art
FIG. 1B
, the portion of the bottom of via
102
which is disposed over target
106
is referred to as “landed”. However, in the aforementioned smaller geometries, portion of vias are often “unlanded”. In Prior Art
FIG. 1B
, portion
110
of via
102
is “unlanded”. That is, portion
110
of the bottom of via
102
does not directly reside over target
106
. As will be discussed below, conventionally unlanded portions of vias (e.g. portion
110
of via
102
) have severe disadvantages associated therewith.
With reference now to Prior Art
FIG. 1C
, an example of a drawback associated with a conventional unlanded via is shown. More particularly, Prior Art
FIG. 1C
illustrates a condition referred to as “gouging”. Gouging, for purposes of the present application, refers to significant excessive and unwanted etching proximate to the unlanded portion of the via. In the example of Prior Art
FIG. 1C
, gouging is schematically depicted in region
112
proximate to unlanded portion
110
of via
102
. As mentioned above, such gouging has significant drawbacks and disadvantages associated therewith. For example, gouging of the substrate proximate to target
106
, creates difficulties in subsequent barrier metal deposition and conductive material filling of via
102
. Additionally, under some circumstances, the gouging may reach or closely approach an underlying layer such as, for example, metal layer (M
1
)
114
. Under such circumstances, it is possible for a short (as depicted by arrow
116
) to occur between the target
106
and the underlying layer
114
. Such shorting will almost certainly adversely affect the semiconductor device in which the short occurs.
One attempt to eliminate gouging and the complications caused thereby is recited in U.S. Pat. No. 6,020,258 entitled “Method for Unlanded Via Etching Using Etch Stop”, to Yew et al. filed Dec. 1, 1997. In the Yew et al. reference, a separate etch stop layer is formed into the substrate, into which the via is to be formed. The separate etch stop layer is formed at approximately the same level as the intended target to prevent the via from being etched substantially deeper than the depth of the target, even if the via is partially unlanded. Although such an approach has utility in certain processes, such an approach is not without problems. As one example, the approach of the Yew et al. reference requires the formation of the etch stop layer within the substrate. Such an etch stop layer requires that the formation of the substrate occur in at least two different steps. That is, at least a first step is required to deposit/grow the substrate onto which the etch stop layer is deposited, and at least a second step is required to deposit/grow the substrate which resides above the etch stop layer. Furthermore, the etch stop layer of the Yew et al. reference may complicate the process of etching through the substrate at locations other than proximate to the target.
Thus, a need exists for a method and apparatus for forming a via wherein the via is not subject to substantial gouging. A further need exists for a method and apparatus which meets the above need and which does not require the formation of a conventional etch stop layer within the substrate. Still another need exists for a method and apparatus which meets the above needs and which is compatible with existing semiconductor fabrication processes.
SUMMARY OF INVENTION
The present invention provides a method and apparatus for forming a via wherein the via is not subject to substantial gouging. The present invention further provides a method and apparatus which achieves the above accomplishment and which does not require the formation of a conventional etch stop layer within the substrate. The present invention also provides a method and apparatus which achieves the above accomplishment and which is compatible with existing semiconductor fabrication processes.
In one embodiment of the present invention, A method and apparatus for reducing gouging during via formation. In one embodiment, the present invention is comprised of a method which includes forming an opening into a substrate. The opening is formed extending into the substrate and terminating on at least a portion of a target to which it is desired to form an electrical connection. After the formation of the opening, the present embodiment lines the opening with a liner material. In this embodiment, the liner material is adapted to at least partially fill a portion of the opening which is not landed on the target. The liner material of the present embodiment prevents substantial further etching of the substrate conventionally caused by the opening being at least partially unlanded on the target. Next, the present embodiment subjects the liner material to an etching process such that the liner material is substantially removed from that region of the target where the opening was landed on the target. In this embodiment, liner material residing in the region where the opening is unlanded prevents further gouging of the substrate proximate to the target.
In yet another embodiment, the present invention includes the steps of the above-described embodiment and further includes the step of depositing a conductive material into the opening. In so doing, the conductive material is electrically coupled to the target. Furthermore, in the present embodiment, the liner material confines the conductive material proximate to the target.
REFERENCES:
patent: 5244837 (1993-09-01), Dennison
patent: 5926738 (1999-07-01), Cronin et al.
patent: 6100183 (2000-08-01), Lu et al.
patent: 6180518 (2001-01-01), Layadi et al.
patent: 6255207 (2001-07-01), Jang
patent: 6399512 (2002-06-01), Blosse et al.
patent: 2002/0155695 (2002-10-01), Lee et al.
Aliyu Yakub
Cheng Wei Hua
Ping Lee Yuan
Yen Daniel
Chartered Semiconductor Manufacturing Limited
Rocchegiani Renzo N
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