Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2002-04-08
2003-10-28
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S232000, C438S275000
Reexamination Certificate
active
06638841
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for reducing a gate length bias, and more particularly to a method for reducing the gate length bias resulting from a photo mask with a high transparency and different etching properties of PMOS gate electrodes and NMOS gate electrodes.
2. Description of the Related Art
Critical dimension control for modern semiconductor processes which are used to form semiconductor devices with tiny features is crucial since it will decide the reliability and electrical properties of the semiconductor devices. For example, the gate length which equals the channel length of the gate electrode of a MOSFET device is one of the most important characteristics since it would hugely affect the reliability and electrical properties of the semiconductor devices.
It is found that the etching properties of a polysilicon layer would vary after it is doped which is a tough problem for critical dimension control of the gate length of a MOSFET device. In a CMOS device, this problem becomes more serious since N type gate electrodes and P type gate electrodes coexist in one device. Accordingly, there is a gate length bias between an N type gate electrode and a P type gate electrode resulting from the different doping of the two types of gate electrodes. It is found that the etching rate of the NMOS gate electrode is faster than that of the PMOS gate electrode due to the lowering of Fermi-level resulting from the N type doping of the NMOS gate electrode. The problem set forth will be more difficult to solve as the transparency of the photo mask used to define the NMOS and PMOS gate electrodes increases or the density of gate electrode pattern decreases in turn. A photo mask with a high transparency will render the photoresist layer used to define the gate electrode pattern looser which will enlarge the gate length bias between the NMOS and PMOS gate electrodes in the etching process.
In view of the drawbacks mentioned with the prior art process, there is a continued need to develop new and improved processes that overcome the disadvantages associated with prior art processes. The advantages of this invention are that it solves the problems mentioned above.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to reduce the gate length bias between the NMOS gate electrodes and the PMOS gate electrodes by using a blanket ion implantation process.
It is another object of this invention to improve the reliability and the electrical stability of a CMOS device.
In the preferred embodiment of this invention, the invention uses a method for reducing a gate length bias, the method comprising: providing a substrate having a P-well and an N-well therein and an undoped conductive layer thereon; performing an N type blanket ion implantation process on the conductive layer to form a lightly doped conductive layer; performing an N type ion implantation process on the portion of the lightly doped conductive layer over the P-well to form a heavily doped conductive layer by using an implantation mask covering the portion of the lightly doped conductive layer over the N-well, where the dosage of the blanket ion implantation process is smaller than the dosage of the ion implantation process; and defining the heavily doped conductive layer and the lightly doped conductive layer separately to form an NMOS gate electrode and a PMOS gate electrode.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
REFERENCES:
patent: 5744845 (1998-04-01), Sayama et al.
patent: 6043544 (2000-03-01), Michael et al.
patent: 6136656 (2000-10-01), Brown et al.
patent: 6362055 (2002-03-01), Lin et al.
patent: 6376323 (2002-04-01), Kim et al.
patent: 6399432 (2002-06-01), Zheng et al.
patent: 6407412 (2002-06-01), Iniewski et al.
Huang Steven
Hwang Ching-Chun
Ko Kai-Jen
Tsai Yuan-Li
Wu Ming-Hui
Lindsay Jr. Walter L.
Niebling John F.
United Microelectronics Corp.
LandOfFree
Method for reducing gate length bias does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for reducing gate length bias, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for reducing gate length bias will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3164143