Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Having heterojunction
Patent
1996-10-25
1998-08-04
Niebling, John
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Having heterojunction
438312, 438320, 438739, 257197, 257200, 148DIG51, 148DIG72, H01L 218222
Patent
active
057893012
ABSTRACT:
This is a method of fabricating a heterojunction bipolar transistor on a wafer. The method can comprise: forming a doped subcollector layer 31 on a semiconducting substrate 30; forming a doped collector layer 32 on top of the collector layer, the collector layer doped same conductivity type as the subcollector layer; forming a doped base epilayer 34 on top of the collector layer, the base epilayer doped conductivity type opposite of the collector layer; forming a doped emitter epilayer 36, the emitter epilayer doped conductivity type opposite of the base layer to form the bipolar transistor; forming a doped emitter cap layer 37 on top of the emitter epilayer, the emitter cap layer doped same conductivity as the emitter epilayer; forming an emitter contact 38 on top of the emitter cap layer; forming a base contact on top of the base layer; forming a collector contact on top of the collector layer; and selective etching the collector layer to produce an undercut 45 beneath the base layer.
REFERENCES:
patent: 4746626 (1988-05-01), Eda et al.
patent: 4825265 (1989-04-01), Lunardi et al.
patent: 4914489 (1990-04-01), Awano
patent: 4967252 (1990-10-01), Awano
patent: 5002901 (1991-03-01), Kurtz et al.
patent: 5019890 (1991-05-01), Ishibashi et al.
patent: 5024958 (1991-06-01), Awano
patent: 5070028 (1991-12-01), Tews et al.
patent: 5124270 (1992-06-01), Morizuka
patent: 5171697 (1992-12-01), Liu et al.
patent: 5266819 (1993-11-01), Chang et al.
patent: 5270223 (1993-12-01), Liu
patent: 5298438 (1994-03-01), Hill
patent: 5344786 (1994-09-01), Bayraktaroglu
patent: 5434091 (1995-07-01), Hill et al.
patent: 5445976 (1995-08-01), Henderson et al.
Niebling John
Pham Long
Triquint Semiconductor, Inc.
LandOfFree
Method for reducing extrinsic base-collector capacitance does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for reducing extrinsic base-collector capacitance, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for reducing extrinsic base-collector capacitance will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1176607