Method for reducing dimensions between patterns on a hardmask

Details Method for reducing dimensions between patterns on a hardmask Method for reducing dimensions between patterns on a hardmask

2008-04-22

2008-04-22

Norton, Nadine G. (Department: 1792)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C439S689000, C439S725000, C216S058000

Reexamination Certificate

active

07361604

ABSTRACT:
A semiconductor manufacturing method that includes depositing a first layer over a substrate, providing a layer of hardmask over the first layer, patterning and defining the hardmask layer to form at least two hardmask structures, wherein each hardmask structure includes at least one substantially vertical sidewall and one substantially horizontal top, and wherein the hardmask structures are separated by a first space, depositing a photo-insensitive material over the at least two hardmask structures and the first layer, wherein an amount of the photo-insensitive material deposited on the top of the hardmask structures is substantially greater than an amount of the photo-insensitive material deposited on the at least one sidewall of the hardmask structures, wherein the hardmask structures with the photo-insensitive layer on the sidewalls thereof are separated by a second space, and wherein the first space is greater than the second space.

REFERENCES:
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patent: 5770510 (1998-06-01), Lin et al.
patent: 5895740 (1999-04-01), Chien et al.
patent: 6100014 (2000-08-01), Lin et al.
patent: 6780782 (2004-08-01), Tsai et al.

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