Semiconductor device manufacturing: process – Making device array and selectively interconnecting
Reexamination Certificate
1999-03-19
2001-03-20
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
C438S624000, C438S618000, C438S633000, C438S637000, C438S692000
Reexamination Certificate
active
06204096
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device containing an interconnection structure comprising conductive wiring on a substrate, and more particularly to a dual damascene process for forming an interconnection structure.
2. Description of the Prior Art
Normally traditional methods for forming interconnection structures conclude the use of subtractive etching or etch back step as the primary metal-patterning techniques. It was also developed as dual damascene process for a practical technique.
One such traditional technique is illustrated in part in
FIGS. 1A
to
1
I, wherein inter-layer dielectrics layer as an oxide layer
112
, such as
FIG. 1A
is formed on semiconductor substrate
111
that is as mono-crystalline silicon. With conductive contacts/vias
113
formed in inter-layer dielectrics layer
112
such as FIG.
1
B.
FIG. 1B
also illustrated inter-layer dielectrics layer
114
is deposited on etching stop layer
113
, such as Silicon Nitride. The interconnection structure comprises conductive contacts/vias
113
and conductive wiring
114
. Then a photoresist mask
115
formed on inter-layer dielectrics layer
114
corresponding to the wiring pattern as shown FIG.
1
C. After etching, as
FIG. 1D
, wiring line pattern is formed using lithography progress. The following step, again a photoresist layer
116
is applied to the resulting wiring pattern shown as
FIG. 1E
, and then the wiring pattern formed as FIG.
1
F. Consequently photoresist mask is removed soon shown as FIG.
1
G. Finally metal is not only deposited onto the surface of above semiconductor device but also filled up the opening as FIG.
1
H.
FIG. 1I
shows the excess metal is removed using typically chemical mechanical polishing process.
Commonly the photoresist layer should be formed thicker for using and owning a long depth of focus in order to expose the entire thickness of the photoresist mask. However, for use of steppers that need high solution, it is difficult in forming quite deep focus in the process. Also it makes thick critical dimension happening and reduces reliability of production.
Moreover, as forming semiconductor integrated circuits devices, a first level interconnect might be formed in contact with a doped region within the substrate of an integrated circuit device. More interconnections are typically formed between the first level wiring line or interconnect and other portions of the integrated circuit device or to structures external to the integrated circuit device.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming integrated circuit devices that substantially achieve estimated semiconductor devices completely.
The present method, in one embodiment, firstly providing a substrate is carried out. Then an interlayer dielectric layer is formed over the substrate. Sequentially an etching stop layer is formed and wherein the etching stop layer is patterned. Thus formation of a dielectric layer over the etching stop is achieved. Also photoresist mask is formed and defined. Therefore an opening for a via is initially formed in a second insulative layer above a first insulative layer with an etching stop layer therein. Consequentially removing the photoresist mask and then depositing a first conductive metal layer are all carried out. Again, photoresist mask is formed and defined. The next step is removing excess parts of the conductive metal. Sequentially the step is depositing a second conductive metal layer. Finally the surface of integrated circuit device is planarized herein.
Apparently the photoresist layer should be formed thicker for using and owning a long depth of focus in order to expose the entire thickness of the photoresist mask according to the present invention. It is for use of steppers that need not high solution, it is much easier in forming quite deep focus in the process. Also it makes thin critical dimension happening and increases reliability of production.
REFERENCES:
patent: 4847183 (1989-07-01), Kruger
patent: 5578523 (1996-11-01), Fiordalice
patent: 5736457 (1998-04-01), Zhao
Huang Chien-Chung
Lai Yeong-Chih
Tsai Yu-Tai
Wu Huang-Hui
Anya Igwe U.
Smith Matthew
United Microelectronics Corp.
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