Method for reducing coupling noise of word lines in a semiconduc

Details Method for reducing coupling noise of word lines in a semiconduc Method for reducing coupling noise of word lines in a semiconduc

1990-02-28

1992-10-13

Popek, Joseph A.

Static information storage and retrieval

Interconnection arrangements

365206, G11C 700

Patent

active

051557002

ABSTRACT:
The higher packing cells memory circuit includes a plurality word line drivers employing a plurality of word lines, a plurality of bit lines, and various decoders. Disclosed is the array method of the word line drivers, which can reduce the pitch between the word line drivers by, for example, arranging word lines in a group to provide a cross-over or to twist the word line is not continuously adjacent to the same neighboring word line, so that the layout of the semiconductor memory array may be easily accomplished. Moreover, the array method of other components of the memory array is suggested.

REFERENCES:
patent: 4586171 (1986-04-01), Fujishima
patent: 4733374 (1988-03-01), Furuyama et al.
patent: 4916661 (1990-04-01), Nawaki et al.
patent: 4977542 (1990-12-01), Matsuda et al.
IEEE International Solid-State Circuits Conference Feb. 19, 1988; pp. 238-239.

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