Method for reducing coherence enforcement by selective...

Details Method for reducing coherence enforcement by selective... Method for reducing coherence enforcement by selective...

2007-08-28

2011-10-11

Ellis, Kevin L (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S135000, C711S144000, C711S145000, C711S154000

Reexamination Certificate

active

08037252

ABSTRACT:
Embodiments of the present invention generally provide techniques and apparatus to reduce the number of memory directory updates during block replacement in a system having a directory-based cache. The system may be implemented to utilize a read/write bit to determine the accessibility of a cache line and limit memory directory updates during block replacement to regions that are determined to be readable and writable by multiple processors.

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