Method for reducing coefficient of thermal expansion in chip att

Details Method for reducing coefficient of thermal expansion in chip att Method for reducing coefficient of thermal expansion in chip att

1997-06-13

2000-10-24

Gallagher, John J.

Fabric (woven, knitted, or nonwoven textile or cloth, etc.)

Woven fabric

Woven fabric including an additional woven fabric layer

29832, 156286, 156295, 1563074, 442251, 442255, 442127FOR, B32B 526, C09J 502

Patent

active

061367338

ABSTRACT:
A simple, inexpensive, drillable, reduced CTE laminate and circuitized structures comprising the reduced CTE laminate, is provided. The reduced CTE laminate comprises: from about 40% to 75%, preferably from about 55% to 65%, by weight resin; from about 0.05% to 0.3%, preferably from about 0.08% to 0.10%, by weight curing agent; from about 25% to 60%, preferably from about 30% to 40%, by weight, woven cloth; from about 1% to 15%, preferably from about 5% to 10%, by volume, non-woven quartz mat. The present invention also generally relates to a method for reducing the CTE of circuitized structures, and to methods for making reduced CTE laminate and circuitized structures comprising reduced CTE laminate. The method for making reduced CTE laminate and laminate structures comprises the following steps: providing non-woven quartz mat; providing a prepreg, preferably B-stage cured to not more than about 40%, preferably not more than 30% of full cure; sandwiching the non-woven quartz mat between two layers of prepreg, and reflowing the resin of the prepreg into the quartz mat. Optionally, the reduced CTE laminate is sandwiched between two layers of metal, preferably copper.

REFERENCES:
patent: 3987230 (1976-10-01), Gaku et al.
patent: 4414264 (1983-11-01), Olson
patent: 4428995 (1984-01-01), Yokono et al.
patent: 4513055 (1985-04-01), Leibowitz
patent: 4650922 (1987-03-01), McPherson
patent: 5217796 (1993-06-01), Kasai et al.
patent: 5350621 (1994-09-01), Yuhas et al.
patent: 5401349 (1995-03-01), Goetz et al.
IBM Research Disclosure N252 Apr. 1985 "Dry Process for Laminating Boards" by Chellis, et al. Apr. 1985.
IBM Technical Disclosure Bulletin Sep. 1984 p. 1964, "Substrate for Surface Solder Devices" by Chellis, et al.
IBM Technical Disclosure Bulletin Apr. 1978, "Prepreg Manufacturing Process" by Haining, et al.

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