Method for reducing cache conflict misses

Details Method for reducing cache conflict misses Method for reducing cache conflict misses

2007-11-20

2007-11-20

Shah, Sanjiv (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S170000, C711S171000, C711S172000

Reexamination Certificate

active

10117020

ABSTRACT:
An invention is provided for reducing cache conflict misses via specific placement of non-split functions and data objects in main memory based on cache size. A cache size of a computer cache memory is determined, and a first data block is placed within a main computer memory. The first data block includes a first sub-block that will be frequently referenced. In addition, the first sub-block ends at a first ending address. A second data block is then placed within the main computer memory. The second data block includes a second sub-block that will be frequently referenced, and is placed such that the second sub-block will be contiguous with the first sub-block in the computer cache memory during execution.

REFERENCES:
patent: 5649143 (1997-07-01), Parady
patent: 6006312 (1999-12-01), Kohn et al.
patent: 2002/0118206 (2002-08-01), Knittel

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