Method for reducing access to main memory using a stack cache

Details Method for reducing access to main memory using a stack cache Method for reducing access to main memory using a stack cache

2006-06-20

2006-06-20

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S136000, C711S144000

Reexamination Certificate

active

07065613

ABSTRACT:
The invention is directed to efficient stack cache logic, which reduces the number of accesses to main memory. More specifically, in one embodiment, the invention prevents writing old line data to main memory when the old line data represents a currently unused area of the cache. In another embodiment, the invention prevents reading previous line data for a new tag from main memory when the new tag represents a currently unused area of the cache.

REFERENCES:
patent: 5893121 (1999-04-01), Ebrahim et al.
patent: 5930820 (1999-07-01), Lynch
patent: 6038643 (2000-03-01), Tremblay et al.
patent: 6151661 (2000-11-01), Adams, III et al.

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