Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-07-25
2006-07-25
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S013000, C703S014000
Reexamination Certificate
active
07082583
ABSTRACT:
An improved method for interconnect delay analysis for VLSI circuits reduces a parasitic graph for moment computation by eliminating one or more nodes in the graph. The elimination process is performed based upon the degree of the nodes. By eliminating nodes in this fashion, the computation complexity is significantly reduced. With this elimination process, resistor loops and crossed loops can also be solved. The order in which the nodes are eliminated is optimized using the depth-first-search method on the parasitic graphs, further reducing the computation complexity. The method provides a consistent functional interface, applicable to different circuit model structures. In addition, the method accounts for coupling capacitance between interconnects.
REFERENCES:
patent: 5379231 (1995-01-01), Pillage et al.
patent: 5469366 (1995-11-01), Yang et al.
patent: 6789237 (2004-09-01), Ismail
Pillage, Lawrence T. et al., “Asymptotic Wafeform Evaluation for Timing Analysis,” IEEE, vol. 9, No. 4, Apr. 1990, pp. 352-366.
Ratzlaff, Curtis L. et al., “RICE: Rapid Interconnect Circuit Evaluation Using AWE,” IEEE, vol. 13, No. 6, Jun. 1994, pp. 763-776.
Bhutani Sandeep
Guo Weiqing
LSI Logic Corporation
Strategic Patent Group
Thompson A. M.
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