Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2005-08-23
2005-08-23
Chin, Stephen (Department: 2634)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C340S003200, C710S025000, C375S376000, C375S371000
Reexamination Certificate
active
06934347
ABSTRACT:
Method for recovering a clock signal from an input data signal in a telecommunications system, that provides for comparing the input data signal with a recovered clock signal in order to control said recovered clock signal generation and provides for generating a plurality of delayed clock signals, obtained by multi-delaying at least a reference signal, said delayed clock signals being phase-shifted with respect to each other. According to the invention, said delayed clock signals show a phase shift with respect to each other, that is nominally constant in time, and, moreover, it is provided for selecting the recovered clock signal among said delayed clock signals.
REFERENCES:
patent: 4789996 (1988-12-01), Butcher
patent: 5081655 (1992-01-01), Long
patent: 5371766 (1994-12-01), Gersbach et al.
patent: 5451894 (1995-09-01), Guo
patent: 5488641 (1996-01-01), Ozkan
patent: 5614855 (1997-03-01), Lee et al.
patent: 5712884 (1998-01-01), Jeong
patent: 5901190 (1999-05-01), Lee
patent: 6247138 (2001-06-01), Tamura et al.
patent: 6484268 (2002-11-01), Tamura et al.
patent: 6636979 (2003-10-01), Reddy et al.
patent: 2002/0101912 (2002-08-01), Phelts et al.
Delay length locked loop in target range tracking Balasubramanian, K. Rajaravivarma, V. Dept. of Comput. Sci. & Eng., Eur. Univ. of Lefke, Mersin, Turkey; This paper appears in: Southeastern Symposium on System Theory, 2001. Proceedings of the 33rd.
A semidigital dual delay-locked up loop Sidiropoulos, S.; Horowitz, M.A.; □□Solid-State Circuits, IEEE Journal of , vol.: 32 , Issue: 11, Nov. 1997; pp.: 1683-1692.
Patent Abstracts of Japan, vol. 011, No. 227, Jul. 23, 1987 corresponding to JP 62 043919 A (Meidensha Electric Mfg. Co. Ltd) dated Feb. 1987.
Patent Abstracts of Japan, vol. 008, No. 059, Mar. 17, 1984 correponding to JP 58 210724 A (Canon KK) dated Dec. 8, 1983.
Maggio Santo
Rutar Massimiliano
Taina Paolo
Alcatel
Chin Stephen
Vartanian Harry
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