Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-10-16
2007-10-16
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
11050232
ABSTRACT:
A method, system and computer program product for performing testing and verification is disclosed. The method includes converting a bias data specification to a driver specification. The driver specification is then parsed into a base constraint and bias file, wherein the base constraint and bias file is suitable for conversion into one of a set comprising a netlist representation and a random simulation representation. A verification framework is selected from among a set comprising a random verification framework using the random simulation representation and a synthesized verification framework using the netlist representation. In response to selecting the random verification framework using the random simulation representation, the random simulation representation is compiled into a parameter database. In response to selecting the synthesized verification framework using the netlist representation, the netlist representation is compiled into a synthesized model. A property of at least one of a set of the synthesized model and the parameter database is tested and verified.
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Baumgartner Jason Raymond
El-Zein Ali S.
Heller Daniel Scott
Roesner Wolfgang
Dillon & Yudell LLP
Dinh Paul
International Business Machines - Corporation
Salys Casimer K.
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