Method for receiver-side clock recovery for digital signals

Details Method for receiver-side clock recovery for digital signals Method for receiver-side clock recovery for digital signals

1996-03-15

1998-01-13

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

36518904, H04L 700

Patent

active

057086869

ABSTRACT:
In a method for receiver-side clock recovery for digital signals having a constant bit rate following cell-structured, asynchronous transmission with pauses of different length between individual cells using the loading state of an FIFO memory into which the received digital signals are written, at the start of a transmission the digital signals are initially read with a received clock into the FIFO memory holding multiple cells of the received signals until the FIFO memory is half filled. The digital signals written into the FIFO memory are read out with a readout clock whose frequency is smaller than the frequency of the received clock. During the readout a signal for controlling the frequency of the readout clock is derived from the respective loading state of the FIFO memory.

REFERENCES:
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patent: 4596026 (1986-06-01), Cease et al.
patent: 4718074 (1988-01-01), Mannas et al.
patent: 5259007 (1993-11-01), Yamamoto
patent: 5289138 (1994-02-01), Wang
patent: 5396492 (1995-03-01), Lien
Martin de Prycker et al., "Asycnchronous Transfer Mode, Solution For Broadband ISDN", published by Ellis Horwood, pp. 115-116.
Ulf Abmus et al., "High-Quality Video and Audio Signal Transmission in a Broadband ISDN based on ATD", Reprinted from EBU-Technical No. 247 (Jun. 1991) pp. 1-7.

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