Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2003-01-29
2004-08-03
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185300, C365S185110
Reexamination Certificate
active
06771545
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to flash memory cell devices and more specifically, to improvements in systems and methods for reading a charge previously stored in a column of charge trapping dielectric flash memory cells that is adjacent to an inactive column.
BACKGROUND OF THE INVENTION
Conventional floating gate flash memory types of EEPROMs (electrically erasable programmable read only memory), utilize a memory cell characterized by a vertical stack of a tunnel oxide (SiO
2
), a polysilicon floating gate over the tunnel oxide, an interlayer dielectric over the floating gate (typically an oxide, nitride, oxide stack), and a control gate over the interlayer dielectric positioned over a crystalline silicon substrate. Within the substrate is a channel region, positioned below the vertical stack, and source and drain diffusions on opposing sides of the channel region.
The floating gate flash memory cell is programmed by inducing hot electron injection from the channel region to the floating gate to create a non volatile negative charge on the floating gate. Hot electron injection can be achieved by applying a drain to source bias along with a high control gate positive voltage. The gate voltage inverts the channel while the drain to source bias accelerates electrons towards the drain. The accelerated electrons gain 5.0 to 6.0 eV of kinetic energy which is more than sufficient to cross the 3.2 eV Si—SiO
2
energy barrier between the channel region and the tunnel oxide. While the electrons are accelerated towards the drain, those electrons which collide with the crystalline lattice are re-directed towards the Si—SiO
2
interface under the influence of the control gate electrical field and gain sufficient energy to cross the barrier.
Once programmed, the negative charge on the floating gate disburses across the semi conductive gate and has the effect of increasing the threshold voltage of the FET characterized by the source region, drain region, channel region, and control gate. During a “read” of the memory cell, the programmed, or non-programmed, state of the memory cell can be detected by detecting the magnitude of the current flowing between the source and drain at a predetermined control gate voltage.
More recently charge trapping dielectric flash memory cell structures have been developed. Each charge trapping dielectric flash memory cell is characterized by a vertical stack of an insulating tunnel layer, a charge trapping dielectric layer, an insulating top oxide layer, and a polysilicon control gate positioned on top of a crystalline silicon substrate.
The cells within the array may be arranged in a matrix such that bit lines are shared by cells within a column, and word lines are shared by cells within a row. More specifically, within the substrate is a channel region associated with each memory cell that is positioned below the vertical stack. One of a plurality of bit line diffusions separates each channel region from an adjacent channel region. The bit line diffusions form the source region and drain region of each cell. Each polysilicon control gate may be a portion of a polysilicon word line extending over the insulating top oxide layer of all cells such that all of the control gates are electrically coupled.
Similar to the floating gate device, the charge trapping dielectric flash memory cell is programmed by inducing hot electron injection from the channel region to the nitride layer to create a non volatile negative charge within charge traps existing in the nitride layer. Again, hot electron injection can be achieved by applying a drain-to-source bias along with a high positive voltage on the control gate. The high voltage on the control gate inverts the channel region while the drain-to-source bias accelerates electrons towards the drain region. The accelerated electrons gain 5.0 to 6.0 eV of kinetic energy which is more than sufficient to cross the 3.2 eV Si—SiO
2
energy barrier between the channel region and the tunnel oxide. While the electrons are accelerated towards the drain region, those electrons which collide with the crystalline lattice are re-directed towards the Si—SiO
2
interface under the influence of the control gate electrical field and have sufficient energy to cross the barrier. Because the nitride layer stores the injected electrons within traps and is otherwise a dielectric, the trapped electrons remain localized within a drain charge storage region that is close to the drain region.
Similarly, a source-to-drain bias may be applied along with a high positive voltage on the control gate to inject hot electrons into a source charge storage region that is close to the source region. For example, grounding the drain region in the presence of a high voltage on the gate and the source region may be used to inject electrons into the source bit charge storage region.
As such, the charge trapping dielectric flash memory cell device can be used to store two bits of data, one in each of the source charge storage region (referred to as the source bit) and the charge storage region (referred to as the drain bit).
Due to the fact that the charge stored in the storage region only increases the threshold voltage in the portion of the channel region beneath the storage region, each of the source bit and the drain bit can be read independently by detecting channel inversion in the region of the channel region beneath each of the source storage region and the drain storage region. To “read” the drain bit, the drain region is grounded while a voltage is applied to the source region and a slightly higher voltage is applied to the gate. As such, the portion of the channel region near the source/channel junction will not invert (because the gate voltage with respect to the source region voltage is insufficient to invert the channel) and current flow at the drain/channel junction can be used to detect the change in threshold voltage caused by the programmed state of the drain bit.
Similarly, to “read” the source bit, the source region is grounded while a voltage is applied to the drain region and a slightly higher voltage is applied to the gate. As such, the portion of the channel region near the drain/channel junction will not invert and current flow at the source/channel junction can be used to detect the change in threshold voltage caused by the programmed state of the source bit.
FIG. 1
shows a block diagram of a conventional array of charge trapping dielectric flash memory cells
16
. Each pair of adjacent bit line diffusions
14
a
-
14
h
form a source region and a drain region for each cell
16
within the column of cells
18
defined by such pair of adjacent bit lines
14
. Each word line
12
a
-
12
e
forms a semiconductor control gate over each cell
16
within the row
20
a
-
20
e
of cells
16
that are defined by such word line
12
.
The above described programming and reading of each charge trapping region of each cell
16
within the array
10
may be accomplish by applying appropriate programming voltage potentials and appropriate read voltage potentials to each bit line diffusion
14
a
-
14
h
and each word line
12
a
-
12
e
to individually program and read selected cells
16
.
Erasing a programmed charge within a cell
16
is performed by coupling bulk erase voltage potentials to each bit line diffusion
14
a
-
14
h
and each word line
12
a
-
12
e
to bulk erase all cells
16
within the array
10
simultaneously. Bulk erase techniques using hot hole injection or the tunneling of the stored charge into the gate or the substrate are known in the art.
A problem associated with such conventional arrays is that certain columns may be inactive. For example, if testing of the array
10
indicates that cells within the columns
18
b
-
18
d
do not operate properly, array control circuits may inactivate such columns
18
b
-
18
d
such that no data is programmed to the cells therein.
A problem associated with inactive columns is over-erasure. While the cells within the inactive columns are not programmed and read, those cells
Ajimine Eric
Chen Pau-ling
Hamilton Darlene G.
He Yi
Hsia Edward
Advanced Micro Devices , Inc.
Hoang Huan
Renner , Otto, Boisselle & Sklar, LLP
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