Method for read cycle interrupts in a dynamic read-only memory

Details Method for read cycle interrupts in a dynamic read-only memory Method for read cycle interrupts in a dynamic read-only memory

1994-08-15

1996-01-23

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Signals

36518905, 365194, 365233, G11C 700, G11C 800

Patent

active

054870380

ABSTRACT:
The invention is a dynamic ROM design for read cycle interrupts. The clock scheme of the improved memory generates a primary start clock. The relatively long pulse time of START when high is provided for setting the latches. This pulse duration is controlled by PCOK or OWDN one shot circuit.
When an address interrupt occurs early in the read cycle, while PCOK or OWDN clock is low, and START is high, these one shot circuits provide a simple means of restarting the cycle by continuing the precharge phase of the cycle with no effect on most of the secondary clocks in the memory. Only those clocks relating to the new address inputs are effected by the early interrupt. This results in less power dissipation and less bus noise.

REFERENCES:
patent: 4953130 (1990-08-01), Houston
patent: 5018111 (1991-05-01), Madland
patent: 5091889 (1992-02-01), Hamano
patent: 5159573 (1992-10-01), Yamada
patent: 5311471 (1994-05-01), Matsumoto

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