Method for re-forming semiconductor layer in TFT-LCD

Details Method for re-forming semiconductor layer in TFT-LCD Method for re-forming semiconductor layer in TFT-LCD

2002-05-07

2003-07-08

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S149000, C438S004000

Reexamination Certificate

active

06589825

ABSTRACT:

The present invention claims the benefit of Korean Patent Application No. 25233/2001 filed in Korea on May 9, 2001, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for re-forming the semiconductor layer of a thin film transistor liquid crystal display (TFT-LCD) device, and more particularly, to a method for re-forming a semiconductor layer of a thin film transistor-liquid crystal display device without damaging a gate by removing a semiconductor layer and a gate insulation film in a manner that a gate is not exposed, and re-depositing an insulation film and a semiconductor layer.
2. Description of the Related Art
In general, a thin film transistor liquid crystal display (TFT-LCD) device is formed such that a metal gate electrode is formed contacting a substrate, a gate insulation film and a semiconductor layer are deposited on the gate electrode, and the semiconductor layer is patterned to form an active region.
In conventional method for depositing the semiconductor layer, if the semiconductor layer was deposited having an electric characteristic different from an expected value due to an abnormality of the process, the substrate including the erroneously deposited semiconductor layer was usually discarded, or only the semiconductor layer was etched and a semiconductor layer was newly deposited, or the semiconductor layer and an insulation film were etched, and then, an insulation film and a semiconductor layer were newly deposited, thereby re-forming the semiconductor layer.
This method for re-forming a semiconductor layer of TFT-LCD device will now be described with reference to the accompanying drawings.
FIGS. 1A through 1C
are sectional views sequentially showing a fabrication process of a method for re-forming a semiconductor layer of a TFT-LCD device in accordance with one conventional art process.
As shown in
FIGS. 1A through 1C
, a method for re-forming a semiconductor layer of a TFT-LCD device in accordance with conventional art includes the steps of depositing a metal on the surface of a substrate
1
, patterning the metal through a photo-etching process to form a gate electrode
2
at a portion thereon, and sequentially depositing a gate insulation film
3
, an amorphous silicon layer
4
, an N
+
amorphous silicon layer
5
doped with a high density N type impurity on the entire upper surface of the substrate
1
(refer to FIG.
1
A), etching the N
+
amorphous silicon layer
5
and the amorphous silicon layer
4
if the deposited amorphous silicon layer
4
or the N
+
amorphous silicon layer are defective, and exposing the gate insulation film
3
(refer to FIG.
1
B); and re-depositing an amorphous silicon layer
6
and an N
+
amorphous silicon layer
7
on the entire upper surface of the resulting structure, to re-form the semiconductor layer (refer to FIG.
1
C). The above method will now be described in more detail.
First, as shown in
FIG. 1A
, a metal is deposited on an entire upper surface of the substrate
1
, on which a photoresist is coated, exposed and developed to form a photoresist pattern thereon.
Next, the exposed metal is etched by an etching process in which the photoresist pattern is used as a mask, so as to form the gate electrode
2
on the substrate
1
.
Then, an insulation film is deposited at an entire upper surface of the resulting structure to form the gate insulation film
3
, on which the amorphous silicon layer
4
is deposited, and then the N
+
amorphous silicon layer
5
is deposited on the entire upper surface thereof.
Therefore, for the sequentially deposited amorphous silicon layer
4
and the N
+
amorphous silicon layer
5
, its electric characteristics may be changed depending on process conditions such as a flow amount of a gas, a pressure and a temperature during deposition. If the electric characteristics are different from expected characteristics, the process is suspended.
That is, as shown in
FIGS. 1A and 1B
, if the deposited amorphous silicon layer
4
and the N
+
amorphous silicon layer
5
are defective, the N
+
amorphous silicon layer
5
and the amorphous silicon layer
4
are sequentially etched through a selective etching process.
At this time, as the amorphous silicon layer
4
is etched, an upper portion of the gate insulation film
3
is exposed to air. As the selective etching process proceeds, the interface of the gate insulation film
3
is also etched during the process of etching of the amorphous silicon layer
4
, even though the etching amount of film
3
is small.
Thus, if the characteristics of the interface of the gate insulation film
3
is changed as the gate insulation film
3
is exposed to air or etched, the electric characteristics of the thin film transistor are degraded.
As shown in
FIG. 1C
, after the amorphous silicon layer
4
and the N+ amorphous silicon layer
5
are etched, the amorphous silicon layer
6
and the N
+
amorphous silicon layer
7
are deposited on the entire upper surface of the gate insulation film
3
, whereby the semiconductor layer is reformed.
Even after the process, if the amorphous silicon layer
6
and the N
+
amorphous silicon layer
7
are defective, the etching and re-deposition process are repeatedly performed. However, if re-formed amorphous silicon layer
6
and N
+
amorphous silicon layer
7
are used, electric characteristics are inevitably degraded (as compared to a normal fabrication process) due to the interface characteristics degradation of the gate insulation film
3
.
FIGS. 2A through 2C
are sectional views sequentially showing a fabrication process of a method for reforming a semiconductor layer of TFT-LCD device in accordance with another conventional art method.
FIGS. 2A through 2C
illustrate another conventional method for re-forming a semiconductor layer of TFT-LCD device that includes the steps of depositing a metal on the surface of a substrate
1
, patterning the metal through a photolithography process to form a gate electrode
2
at one portion of the upper surface of the substrate
1
, and sequentially depositing a gate insulation film
3
, an amorphous silicon layer
4
and an N
+
amorphous silicon layer
5
with high density N type impurity doped thereon at the entire upper surface of the substrate with the gate electrode
2
formed thereon (refer to FIG.
2
A); etching the N
+
amorphous silicon layer
5
, the amorphous silicon layer
4
and the gate insulation film
3
if the deposited amorphous silicon layer
4
and N
+
amorphous silicon layer
5
are defective, thus exposing the gate electrode
2
(refer to FIG.
2
B); and depositing a gate insulation film
8
, an amorphous silicon layer
6
and an N
+
amorphous silicon layer
7
on an entire upper surface of the resulting structure, to re-form a semiconductor layer (refer to FIG.
2
C).
The method for re-forming a semiconductor layer of TFT-LCD device in accordance with another conventional art will now be described in more detail.
First, as shown in
FIG. 2A
, the metal is deposited on an entire upper surface of the substrate
1
, and the metal is patterned by a photolithography process so as to form the gate electrode
2
at one portion of the upper surface of the substrate
1
.
Next, an insulation film is deposited on an entire upper surface of the resulting structure to form the gate insulation film
3
, the amorphous silicon layer
4
is deposited on the entire upper surface of the gate insulation film
3
, and then the N
+
amorphous silicon layer
5
is deposited on the entire upper surface of the amorphous silicon layer
4
.
Accordingly, the electric characteristics of the sequentially deposited amorphous silicon layer
4
and the N
+
amorphous silicon layer
5
, may be changed depending on processing conditions, such as a flow amount of a gas, a pressure and a temperature during deposition. If the electric characteristics are different from expected characteristics, the process

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