Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-01-31
2006-01-31
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06993730
ABSTRACT:
This invention determines whether two circuit models have equivalent functionality. The method allows very fast comparison between two circuits taking advantage of previous work done. Whenever an apparatus associated with the method solves a problem, it stores information that learned during the solution of the problem, in a database. If the apparatus is presented with a new problem of determining equivalence between two portions of two circuits, it checks if it has seen sub-circuits similar to either of the two pieces before. If it has, it uses the knowledge cached during the previous checks to make the new check easier. Checking equivalence of two circuit models involves checking equivalence of many pairs of sub-parts. Even when the subsequent comparisons involve different circuits, it is possible to take advantage of the information acquired during previous equivalence checks.
REFERENCES:
patent: 5243538 (1993-09-01), Okuzawa et al.
patent: 5638381 (1997-06-01), Cho et al.
patent: 5754454 (1998-05-01), Pixley et al.
patent: 5856926 (1999-01-01), Matsumoto et al.
patent: 5909374 (1999-06-01), Matsunaga
patent: 5949691 (1999-09-01), Kurosaka et al.
patent: 6056784 (2000-05-01), Stanion
patent: 6308299 (2001-10-01), Burch et al.
patent: 409198412 (1997-07-01), None
Huang, et al., “AQUILA: An Equivalence Checking System for Large Sequential Designs,”Final Manuscript of Trans. On Computer SIDC-64-R2,pp. 1-36.
Eijk, Cornelis A.J. van, “Formal Methods for the Verification of Digital Cirucits,”CIP-Data Library Technische Universiteit Eindhoven,pp. v-143, 1997.
Mukherjee, et al., “FLOVER: Filtering Oriented Combination Verification Approach”.
Kunz, Wolfgang, “A Novel Framework for Logic Verification in a Synthesis Environment,”IEEE Transactions on Computer-Aided Design of Integrated Circiuts and Systems,vol., 15, No. 1, Jan. 1996, pp. 20-32.
Brand, Daniel, “Verification of Large Synthesized designs,”Proc. Intl. Conf. On Computer-Aided Design(ICCAP), 1993, pp. 534-537.
Kuehlmann, Andreas, “Equivalence Checking Using Cuts and Heaps,” IBM Thomas J. Watson Research Center,Yorktown Heights, NY U.S. A.
Matsumaga, “An Efficient Equivalence Checker for Combination Circuits,” Fujitsu Laboratories, LTD, 33rdDesign Automation Conference, Kawasaki 211-88, Japan.
Pradhan, et al., “VERILAT: Verification Using Logic Augmentation and Transformations,” ICCAD, 1996.
Burch, et al., “Tight Integration of Combination Verification Methods,” Cadence Berkeley Labs,Berkeley, CA.
Bryant, Randal E., “Graph-Based Algorithms for Boolean Function Manipulation,”IEEE Transaction on Computers,vol. C-35, No. 8, Aug. 1986, pp. 677-691.
Foster, Harry, “Techniques for Higher-Performance Boolean Equivalence Verification,”The Hewlett-Packard Journal,Article 3, 1998, pp. 30-38.
Jain, et al., “Advance Verification Techniques Based on Learning,”32ndACM/IEEE Design Automation Conference.
Tafertshofer, et al.,A SAT-Based Implication Engine for Efficient ATPG, Equivalence Checking, and Optimization for Netlists, IEEE,1997.
Kuehlmann, et al., “Error Diagnosis for Transistor-Level Verification,”.
Eijk, C.A.J. van, et al., “Exploiting Functional Dependencies in Finite State Machine Verification,” Design Automation Section, Eindhoven University of Technology.
Eijk, C.A.J. van, et al., “Exploiting Structural Similarities in a BDD-based Verification Method,” Eindoven University of Technology, Department of Electrical Engineering.
Aziz Adnan
Higgins Joseph E.
Singhal Vigyan
Lin Sun James
Pillsbury & Winthrop LLP
Siek Vuthe
Tempus Fugit, Inc.
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