Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reexamination Certificate
1999-10-06
2003-08-26
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
C714S724000, C714S726000, C345S536000, C345S559000, C345S589000
Reexamination Certificate
active
06611941
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a technology of computer manufacturing, particularly to a method of testing RAMDAC.
2. Description of the Related Art
Computer display units use analog signals, whereas computer systems process mainly digital data. Hence, a digital-to-analog (thereafter, DAC) is found in a display control system for converting digital data into analog signals and driving the display units to display images. The digital data inputted into the DAC are from RAM, and are also referred as RAMDAC.
Referring to
FIG. 1
, a block diagram illustrates a conventional display control system. As shown in
FIG. 1
, the display control system
1
comprises: a display controller
10
, RAMDAC
20
, and a display memory (commonly known as video random access memory, or VRAM)
30
. The display controller
10
, RAMDAC
20
and the display memory
30
can be integrated into a single circuit board as a display adapter and coupled to the computer motherboard through an expansion slot. Moreover, the display controller
10
, RAMDAC
20
and the memory display
30
may be built into the computer motherboard.
The display controller
10
serves as an interface between a central processing unit (CPU)
2
and the display control system
1
. In
FIG. 1
, the display controller
10
communicates data through a system bus
3
with the CPU
2
, and outputs horizontal synchronous signals HSYNC and vertical synchronous signals VSYNC for synchronic control of a display unit
4
. Moreover, the data to be displayed onto the display unit
4
(thereafter, display data) are saved in the display memory
30
by the display controller
10
. The display unit
4
can be a cathode ray tube (CRT) display or a flat panel display.
Referring to
FIG. 2
, a block diagram illustrates the detailed RAMDAC
20
of FIG.
1
. In
FIG. 2
, the RAMDAC
20
comprises an address decoder
21
, a color lookup table
22
composed of several registers, and three DACs
23
-
25
. The display data on the address bus A (normally 8-bit data) are decoded by the address decoder
21
and utilized to select the color value stored in a corresponding register of the lookup table
22
. The selected color value is converted into R, G, B video signals by the DACs
23
-
25
to be displayed onto the display unit
4
. For example, 256 registers will be required for the color lookup table
22
to support the 320×200 pixels in 256 colors mode in VGA specification.
Normally, the three primary colors of R, G, and B are each represented in six bits; therefore, each register has a total of 18 bits. The color value stored in each register are provided by the CPU
2
and written therein through a data bus D. Conversely, the color values stored in the registers can be read out through the data bus D. The reading and writing operations are performed by the display controller
10
with a read/write control signal R/W (as shown in FIG.
1
).
However, two requirements have yet to be met for the display control system
1
to display the correct colors. Firstly, the registers have to correctly read, write and save the color values in the color lookup table
22
. And secondly, the DACs
23
-
25
have to correctly convert the digital color values into analog R, G, and B video signals.
SUMMARY OF THE INVENTION
Therefore, the present invention provides a RAMDAC testing method, capable of testing whether registers correctly read, write and save color values and rendering even R, G, and B color layers for visual inspection whether the RAMDACs correctly convert digital color values into analog R, G, and B video signals.
To achieve the above objects, the present invention provides a method of testing a plurality of registers in a RAMDAC, each of the registers having a plurality of bits. First, the bits of the registers are all reset to a first logic state. Then, one logic pattern is written to the registers so as to convert one bit of one of the registers into a second logic state and immediately read out. If the read logic pattern differs from the written logic pattern, an error message will be prompted. The steps are repeated until the testing of each of the bits of the registers is completed.
Moreover, the present invention provides a method for testing digital/analog converters in a RAMDAC. First, a display area of a display unit is divided into three display zones. Then, digital color data are converted by the digital/analog converters into analog video signals where digital color data are sequentially changed. Next, R, G, and B color layers are displayed responsive to the analog video signals in the display zones, respectively. Finally, it is determined whether the display unit displays the R, G, and B color layers evenly.
REFERENCES:
patent: 4244048 (1981-01-01), Tsui
patent: 5083119 (1992-01-01), Trevett et al.
patent: 5442379 (1995-08-01), Bruce et al.
patent: 5875293 (1999-02-01), Bell et al.
Birch & Stewart Kolasch & Birch, LLP
Inventec C'orporation
Moise Emmanuel L.
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