Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-01-19
2010-11-30
Levin, Naum B (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C703S014000
Reexamination Certificate
active
07844927
ABSTRACT:
According to one exemplary embodiment, a method for producing a quality assured semiconductor device model when at least one critical parameter of a semiconductor device process is upgraded includes verifying the quality assured semiconductor device model for consistency against measured data or projected targets. The method further includes verifying the quality assured semiconductor device model for accuracy and consistency when one of a number of critical parameters is varied. The method further includes verifying consistency of the quality assured semiconductor device model against an old semiconductor device model. The method further includes verifying the quality assured semiconductor device model over a range of each of a number of semiconductor device dependencies. The method further includes verifying the quality assured semiconductor device model for digital circuit operation. The method further includes verifying the quality assured semiconductor device model for analog circuit operation. The method further includes verifying convergence of the quality assured semiconductor device model.
REFERENCES:
patent: 5239481 (1993-08-01), Brooks et al.
patent: 5648920 (1997-07-01), Duvvury et al.
patent: 5790436 (1998-08-01), Chen
patent: 5966527 (1999-10-01), Krivokapic et al.
patent: 6141632 (2000-10-01), Smith
patent: 6314390 (2001-11-01), Bittner et al.
patent: 6470230 (2002-10-01), Toprac et al.
patent: 6560568 (2003-05-01), Singhal
patent: 6772035 (2004-08-01), Mouli
patent: 6795800 (2004-09-01), Lee
patent: 6850877 (2005-02-01), Sengupta
patent: 6959271 (2005-10-01), Ballam
patent: 7162402 (2007-01-01), Daems et al.
patent: 7171346 (2007-01-01), Recker et al.
patent: 2003/0200071 (2003-10-01), Zhang et al.
McAndrew; “Statistical modeling for circuit simulation”; Fourth International Symposium on Mar. 24-26, 2003; pp. 357-362.
Huang et al.; “An accurate gate length extraction method for sub-quarter micron MOSFET's”; IEEE Transactions on Electron Devices; vol. 43; No. 6; pp. 958-964; Jun. 1996.
An Judy X.
Icel Ali
Thuruthiyil Ciby T.
Wu Zhi-Yuan
Farjami & Farjami LLP
GLOBALFOUNDRIES Inc.
Levin Naum B
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