Method for Quad-word Storing into 2-way interleaved L1 cache

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

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Details

C711S131000, C711S128000, C711S157000, C711S149000

Reexamination Certificate

active

06233655

ABSTRACT:

FIELD OF THE INVENTION
This invention is related to computers and computer systems and in particular to a method for selectively storing Quad Words into a two-way interleaved L
1
cache with a Double Word wide execution dataflow.
BACKGROUND OF THE INVENTION
In attempting to improve performance in data transfers in complex machines which can have both Quad Word (QW) and Double Word (DW) stores, in the past the apparent solution for using a QW store to cache instead of two double word stores in order to double the data stored per cycle was to increase the data-path size within the execution unit (E-unit) and also the data-path from the E-unit to the BCE (Buffer Control Element which provides a level 1 cache). However, increasing the data-path is expensive in the use of chip area and complexity and results in a much bigger and more complex CPU. We thought it would be desirable to achieve a QW store with a single DW wide data-path and determined how this could be achieved.
SUMMARY OF THE INVENTION
The preferred embodiment permits a Quad Word (QW) store per cycle with a single Double Wide (DW) wide data-path. The implementation provided enables bandwidth improvement without accompanying costs involved in having a wider data bus. Indeed, we now believe that our solution as illustrated by our preferred embodiment could be useful in any processor design that has a small data-bus trying to execute instructions as if there is a wider data-bus, in order to provide better performance.
These and other improvements are set forth in the following detailed description. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.


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