Method for providing self-aligned conductor in a V-groove device

Details Method for providing self-aligned conductor in a V-groove device Method for providing self-aligned conductor in a V-groove device

1979-12-17

1981-10-20

Massie, Jerome W.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156647, 156656, 156657, 1566611, 156662, 204192E, H01L 21308

Patent

active

042959241

ABSTRACT:
A method for providing self-aligned conductors in vertically integrated semiconductor devices which includes providing recesses in the surface of a semiconductor substrate for the fabrication of V-groove devices, providing a conductive layer over the surface and then applying a layer of masking material over the conductive layer to form a planar upper surface, selectively etching the masking material until it remains only in the recesses and then selectively etching the exposed portion of the conductive layer.

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patent: 4105475 (1978-08-01), Jenne
patent: 4120744 (1978-10-01), Payne et al.
patent: 4163988 (1979-08-01), Yeh et al.
patent: 4222816 (1980-09-01), Noble et al.
Lisiak et al., "Optimization of . . . Transistors", IEEE Transaction on Electron Devices, vol. 125, No. 10 (10/78), pp. 1229-1233.
Farzan et al., "Depletion V-Groove . . . Transistors", Solid-State Electronics, vol. 19, No. 4. (4/76), pp. 297-306.
Schiable et al., "Forming . . . Devices", IBM Technical Disclosure Bulletin, vol. 17, No. 10 (3/75), pp. 2893-2894.
Jenne, "Grooves . . . and Performance", Electronics (8/77), pp. 100-106.
Geldermans, "Making . . . of Masks", IBM Technical Disclosure Bulletin, vol. 19, No. 10 (3/77), pp. 3957-3958.
Garnache, "Methal . . . Phase Lines", IBM Technical Disclosure Bulletin, vol. 19, No. 7 (12/76), pp. 2471-2472.
Jambotkar, "Power . . . Transistor", IBM Technical Disclosure Bulletin, vol. 21, No. 5 (10/78), pp. 1884-1885.

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