Method for providing offset mask for pseudo-noise sequence gener

Details Method for providing offset mask for pseudo-noise sequence gener Method for providing offset mask for pseudo-noise sequence gener

1997-07-08

1999-12-21

Chin, Stephen

Pulse or digital communications

Repeaters

Testing

375367, 364717, H04K 100, H04L 700, G06F 102

Patent

active

060058889

ABSTRACT:
A method, executed in a microprocessor, for providing a shift-and-add mask, M=m.sub.1, m.sub.2, . . . , m.sub.N-1, m.sub.N, for a pseudo-noise sequence generator ("PNSG"). The PNSG generates a first pseudo-noise ("PN") code, and has N stages, each stage being at one of two states. The PNSG also has an associated shifter for generating a shifted PN code which is the same code as the first PN code, but delayed by K chips. The shifted PN code is generated as the inner product of the shift-and-add mask with the states of the stages of the PNSG. According to the inventive method, a value of K is provided, and it is determined whether K is 0. If K is 0, M is provided such that m.sub.N =1 and, for all n.noteq.N, m.sub.n =0. However, if K is not 0, it is determined whether K is greater than N. If K is greater than N, the remainder, R, of the division D.sup.K-1 /f(D), is determined, where

REFERENCES:
patent: 5228054 (1993-07-01), Rueth et al.
patent: 5532695 (1996-07-01), Park et al.
patent: 5835528 (1998-11-01), Barron

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