Method for providing memory cells capable of allowing...

Details Method for providing memory cells capable of allowing... Method for providing memory cells capable of allowing...

2007-06-26

2007-06-26

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

10904226

ABSTRACT:
A method for providing memory cells that allow multiple variations of metal level assignments for bitlines and wordlines is disclosed. A memory cell includes two cell elements. The first and second cell elements are identically processed up to a metal-1 layer. The first cell element is subsequently processed with bitlines on a metal-2 layer and wordlines on a metal-3 layer. Next, the second cell element is processed with bitlines on the metal-3 layer and wordlines on the metal-2 layer.

REFERENCES:
patent: 6950355 (2005-09-01), Battacharya et al.

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