Method for providing layout design and photo mask

Details Method for providing layout design and photo mask Method for providing layout design and photo mask

2008-05-20

2008-05-20

Garbowski, Leigh Marie (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07376931

ABSTRACT:
A method for providing the layout design of semiconductor integrated circuit that is capable of promoting the reduction of the circuit pattern area is provided. A hole pattern is disposed at the mesh point which is an intersecting point of mutually orthogonal virtual grid lines and another hole pattern is not disposed at the adjacent mesh point that is the closed mesh point having the hole pattern thereon.

REFERENCES:
patent: 6795956 (2004-09-01), Hokari
patent: 6838216 (2005-01-01), Griesinger et al.
patent: 6839890 (2005-01-01), Sugita et al.
patent: 6964032 (2005-11-01), Liebmann et al.
patent: 7107573 (2006-09-01), Yamazoe et al.
patent: 2002/0177050 (2002-11-01), Tanaka
patent: 11-135402 (1999-05-01), None

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