Method for providing clock-net aware dummy metal using dummy...

Details Method for providing clock-net aware dummy metal using dummy... Method for providing clock-net aware dummy metal using dummy...

2006-02-28

2006-02-28

Garbowski, Leigh M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07007259

ABSTRACT:
A method and system is disclosed for inserting dummy metal into a circuit design, which includes a plurality of objects and clock nets. Aspects of the invention include identifying free spaces on each layer of the chip design suitable for dummy metal insertion, wherein the free spaces are referred to as dummy regions. Thereafter, the dummy regions are prioritized such that the dummy regions located adjacent to clock nets are filled with dummy metal last. In a preferred embodiment, the dummy regions are further prioritized such that the dummy regions adjacent to wider clock nets are filled with dummy metal after dummy regions that are located adjacent to narrower clock nets.

REFERENCES:
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patent: 6446248 (2002-09-01), Solomon et al.
patent: 6751785 (2004-06-01), Oh
patent: 6815811 (2004-11-01), Ozawa et al.
patent: 2003/0177464 (2003-09-01), Takechi et al.
patent: 2003/0204832 (2003-10-01), Matumoto
patent: 2003/0229479 (2003-12-01), Smith et al.
Liu, George Y. et al., “Chip-Level CMP Modeling and Smart Dummy for HDP and Conformal CVD Films,” CMP-MIC Conference, Feb. 11-12, 1999, pp. 120-127.

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