Method for providing and operating upgradeable cache circuitry

Details Method for providing and operating upgradeable cache circuitry Method for providing and operating upgradeable cache circuitry

1998-09-21

2000-09-12

Peikari, B. James

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Addressing extended or expanded memory

711141, 711122, 711 3, 711144, 711170, 710 13, G06F 1208

Patent

active

061191973

ABSTRACT:
An upgradeable cache circuit is described which automatically routes those control signals necessary to maintain cache coherency in a computer system having a processor (with integrated L1 cache) coupled with main memory by a controller. The cache circuit includes an L2 cache module connector and a high speed multiplexer having minimal propagation delay. The multiplexer selects one of two sets of control signals to route to and from the processor, controller and cache circuit, corresponding to the presence or absence of an L2 cache module in the cache module connector.

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