Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1998-09-14
2002-10-01
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S152000, C711S163000, C711S164000
Reexamination Certificate
active
06460121
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains in general to reading a memory cell in a computer system having a memory shared between multiple processing nodes, and more particularly, but not by way of limitation, to a method for performing a sixty-four bit atomic memory read on a thirty-two bit processor using a sixty-four bit compare-exchange instruction primitive.
BACKGROUND OF THE INVENTION
In a shared memory computing environment wherein a plurality of processing nodes have access to a shared memory cell, many types of situations may arise which can compromise data integrity. One such situation occurs when a processor in one of the processing nodes attempts to read a sixty-four bit memory cell using two, thirty-two bit read operations. Typically, if a processor needs to read the sixty-four bit memory cell, the processor performs a single atomic sixty-four bit memory read operation. In certain situations, however, the processor is unable to perform a single sixty-four bit read operation. Instead, the processor first reads either the low-order thirty-two bits or the high-order thirty-two bits in a first read operation and then reads the remaining high-order thirty-two bits or the low-order thirty-two bits, respectively, in a second distinct read operation.
There are various reasons for the processor to perform two thirty-two bit reads instead of a single sixty-four bit read. For instance, a communication bus used by the processor to access the memory cell may only have the capacity to communicate either the low-order thirty-two bits or the high-order thirty-two bits at a time. In another instance, the communication bus may have the capacity to communicate both the low-order thirty-two bits and the high-order thirty-two bits at the same time but the processor may only have a register, used in the read operation, large enough to store either the low-order thirty-two bits or the high order thirty two bits. In these instances, the processor performs two separate accesses to the memory cell in order to read the entire contents of the memory cell.
A problem arises, however, if a processor other than the processor performing the read operation modifies the contents of the memory cell after the original processor performing the read operation reads the low-order thirty-two bits but before the original processor reads the high-order thirty-two bits. This situation occurs as a result of each processing node operating asynchronously at various speeds with different priorities to access system resources including the memory cell. To prevent this problem from occurring, the processor can be programmed to perform an atomic read operation which locks out other processors from writing to the memory cell until after the reading processor performs both the low-order and high-order reads. There are processors, however, which are not programmed to perform such an atomic read operation.
In situations where the processor must perform a low-order and a high-order read operation and an atomic read operation is unavailable, other methods have been used to perform an atomic read operation. Operating System synchronization techniques have been used as has the implementation of mutual exclusion and semaphore objects to provide an atomic sixty-four bit read operation on two adjacent thirty-two bit data parts. Another method is to utilize floating point registers in the read operation. These methods, however, are either complex or consume a relatively larger number of clock cycles. For example, the use of floating point registers requires that the floating point state be saved and restored to preserve floating state on context switches.
Therefore, it would be advantageous to devise a method to provide a simple mechanism by which an atomic sixty-four bit read operation can be performed in situations where two, thirty-two bit read operations are required.
SUMMARY OF THE INVENTION
The present invention comprises a method for performing an atomic read of a memory cell shared by a plurality of processing nodes. A plurality of data parts of the memory cell are loaded into a respective first plurality of registers and an atomic compare and exchange operation is executed on the memory cell. The first plurality of registers is read and concatenated. The compare and exchange operation results in a value formed by concatenating the first plurality of registers being equal to the value of the memory cell.
In a first embodiment of the present invention, a low-order data part of the memory cell is loaded into registers A and B and a high-order data part of the memory cell is loaded into registers D and C. An atomic compare and exchange operation is executed on the memory cell and register A and register D are read. The contents of the memory cell is equal to a value formed by the concatenation of register D with register A.
In a second embodiment of the present invention, the contents of register A is loaded into register B and the contents or register D is loaded into register C. An atomic compare and exchange operation is executed on the memory cell and register A and register D are read. The contents of the memory cell is equal to a value formed by the concatenation of register D to register A.
In a third embodiment of the present invention, register A is loaded with a known value wherein, the value is known never to exist in the low-order data part of the memory cell and register D is loaded with a value wherein, the value is known never to exist in the high-order data part of the memory cell. An atomic compare and exchange operation is executed on the memory cell and register A and register D are read. The contents of the memory cell is formed by the concatenation of register D with register A.
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Compaq Information Technologies Group L.P.
Fletcher, Yoder, and Van Someren
Kim Matthew
Vital Pierre M.
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