Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
1997-11-17
2001-02-06
Gossage, Glenn (Department: 2759)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S105000, C711S170000, C713S401000, C713S501000, C365S194000, C365S233100
Reexamination Certificate
active
06185664
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to memory systems for computers, and more particularly to the design of a memory system that provides variable memory latency for read and/or write accesses to a synchronously accessed memory.
2. Related Art
New memory system designs have been developed to keep pace with rapid increases in processor clock speeds. As processors get faster, memory systems are under increasing pressure to provide data at faster rates to keep up with the processors. This has recently led to the development of new memory system designs. Latencies for memory accesses have been dramatically decreased by using page mode and extended data out (EDO) memory designs, which achieve a high burst rate and low latencies within a single page of memory. Another recent innovation is to incorporate a synchronous clocked interface into a memory chip, thereby allowing data from within the same page of memory to be clocked out of the memory in a continuous stream using the processor clock. Such memory chips, with clocked interfaces are known as synchronous random access memories.
RAMBUS™ and SYNCLINK™ have been developed to govern the transfer of data between memory and processor using such clocked interfaces. (Rambus is a trademark of Rambus, Inc. of Mountain View, Calif. Synclink is a trademark of the Microgate Corporation of Austin, Tex. SYNCLINK™, which will be known as Institute for Electrical and Electronic Engineers (IEEE) Standard 1596.7, specifies an architecture that supports a 64 megabit (m-bit) memory with a data transfer rate of 1.6 gigabytes per second. SYNCLINK™ packetizes and pipelines the address, commands, and timing, and adds features that significantly increase the data bus speed, thereby providing fast memory access without losing the ability to move quickly from row to row or to obtain bursts of data. In the IEEE standard, a 10-bit upper bus is used for command and address transmission, and an 18-bit lower bus is used for data signals.
As processor clock speeds continue to increase, it is becoming increasingly harder for memories with clocked interfaces to keep pace with processor clock speeds. More than one clock cycle of time may be required to read from or write to a synchronous memory. Furthermore, the amount of time required to access a memory may depend upon the latency of a particular memory chip, and this latency can vary as different memory chips are included in a memory system. This makes it hard to design a memory architecture that can flexibly accommodate different memory chips.
What is needed is a memory system including a synchronous interface between processor and memory that provides more than one clock cycle of time for read and/or write accesses to the memory.
Additionally, what is needed is a memory system that provides a configurable latency for read and write accesses to a synchronously accessed memory in order to allow the memory system to operate with different memory devices and/or different processor clock speeds.
SUMMARY
One embodiment of the present invention provides a memory system that allows more than one cycle of memory latency for accesses to a synchronously accessed memory. In this embodiment, the memory system includes a memory with a clocked interface and a corresponding clock input. It also includes an output register for storing data outputted from the memory during a read operation. The output register and the memory are coupled together by a data path, for transferring data between the memory and the output register. In this embodiment, the memory system further includes a clock signal coupled to the clocked interface of the memory. The clock signal feeds through a delay element into a clock input of the output register. This causes the output register to receive a delayed clock signal, thereby providing more than one clock cycle of time for data to be read from the memory and latched in the output register. In another embodiment, the present invention provides an input register, for inputting data during write operations. This input register similarly receives a delayed clock signal, which functions as an advanced or early clock signal from the preceding clock cycle to provide more than one clock cycle of latency for write accesses to memory.
In one embodiment of the present invention, the delayed clock signal for the input system and the delayed clock signal for the output register have the same delay value.
In one embodiment of the present invention, the delay element may include a variable delay, which can be selectively configured to produce different delays to flexibly accommodate different memory latencies and processor speeds.
In another embodiment, the memory may include a plurality of memory modules.
Yet another embodiment of the present invention provides a memory controller that allows for more than one clock cycle of memory latency for accesses to a memory. In this embodiment, the memory controller includes: a processor interface, for coupling to a processor; an input register including a clock input, for storing data to be inputted into the memory during a write operation; and an output register including a clock input, for storing data outputted from the memory during a read operation. The memory controller may also include a data path coupled between the processor interface and the input and output registers, for transferring data between the processor interface and the input and output registers. The memory controller may additionally include a controller coupled to the processor interface, the input register and the output register, for controlling the transfer of data between a processor coupled to the processor interface and a memory coupled to the input and output registers. This controller may include a first delay element, with an input coupled to a clock signal, and an output coupled to the output register, so that the output register receives a delayed clock signal.
In another embodiment, the controller may include a second delay element, including an input coupled to the clock signal, and an output coupled to the output register, so that the output register receives a delayed clock signal.
In another embodiment, the first delay element may include a variable delay, which can be selectively configured to produce different delays.
In yet another embodiment, the memory controller may include a control interface coupled to the controller for providing control signals to the memory.
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patent: 5608896 (1997-03-01), Vogley
patent: 5655105 (1997-08-01), McLaury
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patent: 5923611 (1999-07-01), Ryan
Gossage Glenn
Micro)n Technology, Inc.
Park & Vaughan LLP
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