Electronic digital logic circuitry – Multifunctional or programmable – Array
Patent
1996-05-24
1998-08-04
Westin, Edward P.
Electronic digital logic circuitry
Multifunctional or programmable
Array
326 39, 326 38, H03K 19082, H03K 19173
Patent
active
057899398
ABSTRACT:
A very high-density complex programmable logic device (CPLD) has a plurality of hierarchical signal paths. The lowest level of the hierarchy is independent from all higher levels. Similarly, an intermediate level is independent from all higher levels and utilizes only resources of the CPLD associated with the lowest and intermediate hierarchical levels. The first hierarchical level resources include a programmable logic block having a plurality of input lines and a plurality of output lines, and a programmable block switch matrix connected to the plurality of input lines of the programmable logic block. The second hierarchical level resources include a programmable segment switch matrix connected to a plurality of input lines of the programmable block switch matrix. The CPLD in addition includes a third hierarchical level circuit having third hierarchial level resources connected to the second hierarchical level resources where a third hierarchical level signal path utilizes the third, second, and first hierarchical level resources. The third hierarchical level resources include a programmable global switch matrix having global switch matrix lines programmably connected to and disconnected from lines of the programmable segment switch matrix.
REFERENCES:
patent: 4758746 (1988-07-01), Birkner et al.
patent: 4789951 (1988-12-01), Birkner et al.
patent: 5130574 (1992-07-01), Shen et al.
patent: 5191243 (1993-03-01), Shen et al.
patent: 5204556 (1993-04-01), Shankar
patent: 5220214 (1993-06-01), Pedersen
patent: 5258668 (1993-11-01), Cliff et al.
patent: 5260610 (1993-11-01), Pedersen et al.
patent: 5260611 (1993-11-01), Cliff et al.
patent: 5341044 (1994-08-01), Ahanin et al.
patent: 5371422 (1994-12-01), Patel et al.
patent: 5376844 (1994-12-01), Pedersen et al.
patent: 5394033 (1995-02-01), Tsui et al.
patent: 5521529 (1996-05-01), Agrawal et al.
patent: 5552722 (1996-09-01), Kean
Publication entitled "A High Performance FPGA with Hierarchical Interconnection Structure", 1994 IEEE International Symposium on Circuits and Systems, London May 30-Jun. 2, 1994, vol. 4 of 6, 30 May 1994, Institute of Electrical and Electronics Engineers, pp. 239-242.
Agrawal Om P.
Sharpe-Geisler Bradley A.
Advanced Micro Devices , Inc.
Kwok Edward C.
Roseen Richard
Westin Edward P.
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