Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-08-06
2001-04-17
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S340000, C257S364000, C257S407000, C438S257000
Reexamination Certificate
active
06218689
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to flash memory devices, and more particularly to NAND-type flash memory devices.
BACKGROUND OF THE INVENTION
Semiconductor flash memory devices include NAND-type flash memory devices. Such memory devices typically comprise a high density core region and a low density peripheral region on a single substrate. The memory cells within the core region are coupled together in a NAND-type circuit configuration, as illustrated in
FIGS. 1A and 1B
.
FIG. 1A
illustrates a circuit schematic diagram of the core region
11
while
FIG. 1B
illustrates a plan view of the core region
11
. The core region
11
includes a memory cell region
22
which is bounded on one side by a drain select transistor portion
24
and bounded on another side by a source select transistor portion
26
. Each of the select transistor portions
24
and
26
contain select gate transistors
24
a
-
24
c
and
26
a
-
26
c
, respectively, which operate to selectively activate a desired bit line.
FIG. 1C
illustrates a cross-section of conventional stack structures of a select transistor
100
and a memory cell
150
in the core region
11
. The stack structure
150
of the memory cell includes a tunnel oxide
104
on a substrate
102
and a floating gate
106
composed of polysilicon on the tunnel oxide
104
. The control gate comprises a polysilicon layer
110
and a tungsten silicide layer
112
on the polysilicon layer
110
. A dielectric layer insulates the floating gate
106
from the control gate
110
and
112
. The control gate
110
and
112
is coupled to a word line. A cap layer
114
composed of silicon oxynitride resides on the control gate
110
and
112
and provides an anti-reflective coating at masking.
The stack structure
100
of the select transistor comprises a select gate oxide
116
on the substrate
102
. A select gate
118
is on the select gate oxide
116
. Like the memory cell stack structure
150
, the control gate of the select transistor includes a polysilicon layer
122
and a tungsten silicide layer
124
. A dielectric layer
120
insulates the select gate
118
from the control gate
122
and
124
. The stack structure
100
is topped by a silicon oxynitride layer
126
.
Typically, the floating gate
106
of the memory cell stack structure
150
and the select gate
118
of the select transistor stack structure
100
are formed from a single in-situ doped polysilicon layer. Subsequent masking and etching provides the resulting floating gate
106
and the select gate
118
. In order to properly perform the programming and erasure of the memory cell, this single polysilicon layer must be conductive. It may be rendered conductive by using doped amorphous silicon for the single polysilicon layer. The dopant level of the single polysilicon layer is critical in the performance of the memory cell and thus the semiconductor device as a whole.
However, there are two conflicting factors in determining the level of dopant for the single polysilicon layer. If the dopant level is too low, this will cause the control gate contact resistance of the select transistor to become too high since the select gate
118
is connected to the control gate
122
and
124
via an interconnect (not shown). This causes the select transistor word line resistance to also become too high, resulting in a slower circuit performance. If the dopant level is too high, some of the dopant will contaminate the tunnel oxide
104
of the memory cell, which causes the surface of the floating gate
106
and tunnel oxide
104
interface to be rough. The rough interface leads to a high local electric field and a lower oxide dielectric strength. This causes reliability problems and a charge gain/loss problem in the programming and erasure of the memory cell.
Accordingly, there exists a need for a method and NAND-type flash memory device for providing a polysilicon dopant level which avoids both the select transistor word line high resistance and the charge gain/loss problems. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a method and a NAND-type flash memory device. The method includes forming a select gate oxide layer in a select transistor area of a substrate and a tunnel oxide layer in a memory cell area of the substrate; forming a doped amorphous silicon layer on the select gate oxide layer and the tunnel oxide layer, the doped amorphous silicon layer having a dopant level which simultaneously avoids a select transistor word line high resistance problem and a charge gain/charge loss problem; forming an insulating layer on the doped amorphous silicon layer; forming a control gate layer on the insulating layer; and etching at least the doped amorphous silicon layer, the insulating layer, and the control gate layer to form at least one memory cell stack structure and at least one select transistor stack structure. In a preferred embodiment, the polysilicon layer which forms both the floating gate of the flash memory cell and the select gate of the select transistor of the device is doped with between approximately 5×10
18
and 8×10
19
ions/cm
3
of phosphorus. With this dopant level, the contact resistance of the select transistor's control gate is low, thus keeping the word line resistivity of the device low. Simultaneously, contamination of the tunnel oxide of the flash memory cell by the dopant is limited, allowing for the interface between the floating gate and the tunnel oxide to be smooth, which prevents charge gain/loss problems. Thus, the reliability of the device is increased.
REFERENCES:
patent: 4597159 (1986-07-01), Usami et al.
patent: 4899205 (1990-02-01), Hamdy et al.
patent: 5424232 (1995-06-01), Yamauchi
patent: 5511020 (1996-04-01), Hue et al.
patent: 5677867 (1997-10-01), Hazani
patent: 5866930 (1999-02-01), Saida et al.
patent: 6023085 (2000-02-01), Fang
patent: 0612108 (1994-08-01), None
patent: 0663695 (1995-07-01), None
Au Kenneth Wo-Wai
Chang Kent Kuohua
Fang Hao
Advanced Micro Devices , Inc.
Malsawma Lex H.
Sawyer Law Group LLP
Smith Matthew
LandOfFree
Method for providing a dopant level for polysilicon for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for providing a dopant level for polysilicon for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for providing a dopant level for polysilicon for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2538622