Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2006-08-25
2010-11-23
Gurley, Lynne A (Department: 2811)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S279000, C257SE21661, C430S394000
Reexamination Certificate
active
07838407
ABSTRACT:
A gate of a transistor in an integrated circuit is protected against the production of an interconnection terminal for a source/drain region. The transistor includes a substrate, at least one active zone formed in the substrate, at least one insulating zone formed in the substrate and a gate, the gate being formed above an active zone. A dielectric layer is formed on the transistor, the dielectric layer covering the gate. The dielectric layer is then etched while leaving it remaining at least on the gate so that the gate is electrically insulated from other elements formed above the dielectric layer. This etching is preferably carried out using a mask which was used for fabricating the gate and a mask which was used for fabricating the insulating zone.
REFERENCES:
patent: 5384287 (1995-01-01), Fukase et al.
patent: 5710073 (1998-01-01), Jeng et al.
patent: 6689655 (2004-02-01), Coronel et al.
patent: 6833575 (2004-12-01), Parekh et al.
patent: 2003/0130439 (2003-07-01), Clough et al.
patent: 2004/0067629 (2004-04-01), Beaman
patent: 2005/0032314 (2005-02-01), Parekh et al.
Preliminary French Search Report, FR 05 08835, dated Jun. 1, 2006.
Gardere Wynne & Sewell LLP
Gurley Lynne A
Matthews Colleen A
STMicroelectronics (Crolles 2) SAS
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